| Message ID | 20220329180238.1380552-1-sean.anderson@seco.com |
|---|---|
| State | Changes Requested |
| Delegated to: | Tom Rini |
| Headers | show |
| Series | treewide: Enable SPL_SEPARATE_BSS if SPL_BSS_START_ADDR is used | expand |
On Tue, Mar 29, 2022 at 02:02:38PM -0400, Sean Anderson wrote: > If .bss does not immediately follow the end of the image, then > CONFIG_SPL_SEPARATE_BSS must be selected. Typically, the location of bss > is specified by using CONFIG_SPL_BSS_START_ADDR in a linker script. On > these arches, CONFIG_SPL_SEPARATE_BSS should be enabled. If there is an > option to use an alternate boot script (e.g. CONFIG_SPL_LDSCRIPT is just > a default), just imply. If there is not, select. > > Signed-off-by: Sean Anderson <sean.anderson@seco.com> This gives "WARNING: unmet direct dependencies detected for SPL_SEPARATE_BSS" for: boston32r2 boston32r2el boston32r6 boston32r6el malta maltael imgtec_xilfpga ap121 ap143 ap152 tplink_wdr4300 netgear_cg3100d_ram comtrend_ar5315u_ram comtrend_vr3032u_ram comtrend_ar5387un_ram sagem_f@st1704_ram comtrend_ct5361_ram huawei_hg556a_ram sfr_nb4-ser_ram netgear_dgnd3700v2_ram comtrend_wap5813n_ram bcm968380gerg_ram mscc_jr2 mscc_luton mscc_ocelot mscc_serval mscc_servalt pic32mzdask boston64r2 boston64r2el boston64r6 boston64r6el malta64 malta64el octeon_ebb7304 octeon_nic23 ae350_rv32 ae350_rv32_xip ae350_rv64 ae350_rv64_xip qemu-riscv32 qemu-riscv32_smode qemu-riscv64 qemu-riscv64_smode microchip_mpfs_icicle openpiton_riscv64 sipeed_maix_bitm sipeed_maix_smode
diff --git a/arch/Kconfig b/arch/Kconfig index 1b35fda64c..e6da7ea028 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -85,6 +85,7 @@ config MIPS select HAVE_ARCH_IOREMAP select HAVE_PRIVATE_LIBGCC select SUPPORT_OF_CONTROL + select SPL_SEPARATE_BSS config NDS32 bool "NDS32 architecture" @@ -112,6 +113,7 @@ config RISCV select SUPPORT_OF_CONTROL select OF_CONTROL select DM + select SPL_SEPARATE_BSS imply DM_SERIAL imply DM_ETH imply DM_EVENT diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 777d318c5d..1909afc43a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -8,6 +8,7 @@ config ARM64 bool select PHYS_64BIT select SYS_CACHE_SHIFT_6 + imply SPL_SEPARATE_BSS config ARM64_CRC32 bool "Enable support for CRC32 instruction" @@ -267,6 +268,7 @@ config CPU_ARM926EJS bool select SYS_CACHE_SHIFT_5 imply SYS_ARM_MMU + imply SPL_SEPARATE_BSS config CPU_ARM946ES bool @@ -277,6 +279,7 @@ config CPU_ARM1136 bool select SYS_CACHE_SHIFT_5 imply SYS_ARM_MMU + imply SPL_SEPARATE_BSS config CPU_ARM1176 bool @@ -624,6 +627,7 @@ config ARCH_ORION5X bool "Marvell Orion" select CPU_ARM926EJS select GPIO_EXTRA_HEADER + select SPL_SEPARATE_BSS config TARGET_STV0991 bool "Support stv0991" @@ -814,6 +818,7 @@ config ARCH_OMAP2PLUS imply TI_SYSC if DM && OF_CONTROL imply FIT imply DM_EVENT + imply SPL_SEPARATE_BSS config ARCH_MESON bool "Amlogic Meson" @@ -954,6 +959,7 @@ config ARCH_MX6 select SYS_FSL_SEC_LE imply MXC_GPIO imply SYS_THUMB_BUILD + imply SPL_SEPARATE_BSS if ARCH_MX6 config SPL_LDSCRIPT
If .bss does not immediately follow the end of the image, then CONFIG_SPL_SEPARATE_BSS must be selected. Typically, the location of bss is specified by using CONFIG_SPL_BSS_START_ADDR in a linker script. On these arches, CONFIG_SPL_SEPARATE_BSS should be enabled. If there is an option to use an alternate boot script (e.g. CONFIG_SPL_LDSCRIPT is just a default), just imply. If there is not, select. Signed-off-by: Sean Anderson <sean.anderson@seco.com> --- arch/Kconfig | 2 ++ arch/arm/Kconfig | 6 ++++++ 2 files changed, 8 insertions(+)