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[188.217.56.61]) by smtp.gmail.com with ESMTPSA id v10-20020a170906380a00b006a68610908asm1022219ejc.24.2022.03.16.08.28.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 08:28:19 -0700 (PDT) From: Tommaso Merciai To: Cc: tommaso.merciai@amarulasolutions.com, Stefano Babic , Fabio Estevam , "NXP i.MX U-Boot Team" , Peng Fan , Ye Li , Alice Guo , Andrey Zhizhikin , Marek Vasut , =?utf-8?q?Marek_Beh=C3=BAn?= , u-boot@lists.denx.de Subject: [PATCH v2 4/9] arm: imx: imx8mm: add enable_pwm_clk function Date: Wed, 16 Mar 2022 16:27:40 +0100 Message-Id: <20220316152746.47768-5-tommaso.merciai@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220316152746.47768-1-tommaso.merciai@amarulasolutions.com> References: <20220316152746.47768-1-tommaso.merciai@amarulasolutions.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Add function enable_pwm_clk into in clock_imx8mm.c. This function first configure, then enable pwm clock from clock control register. The following configuration is used: source(0) -> 24 MHz ref clock div(0) -> no division for this clock References: - iMX8MMRM.pdf p 303 Signed-off-by: Tommaso Merciai --- Changes since v1: - Fix enable_pwm_clk function implementation. Now is generic for all pwm clks arch/arm/mach-imx/imx8m/clock_imx8mm.c | 53 ++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index 49945faf2c..ffb9456607 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -313,6 +313,59 @@ void enable_usboh3_clk(unsigned int enable) } } +void enable_pwm_clk(u32 index, unsigned char enable) +{ + switch (index) { + case 0: + if (enable) { + clock_enable(CCGR_PWM1, false); + clock_set_target_val(PWM1_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(0) | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1)); + clock_enable(CCGR_PWM1, true); + } else { + clock_enable(CCGR_PWM1, false); + } + return; + case 1: + if (enable) { + clock_enable(CCGR_PWM2, false); + clock_set_target_val(PWM2_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(0) | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1)); + clock_enable(CCGR_PWM2, true); + } else { + clock_enable(CCGR_PWM2, false); + } + return; + case 2: + if (enable) { + clock_enable(CCGR_PWM3, false); + clock_set_target_val(PWM3_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(0) | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1)); + clock_enable(CCGR_PWM3, true); + } else { + clock_enable(CCGR_PWM3, false); + } + return; + case 3: + if (enable) { + clock_enable(CCGR_PWM4, false); + clock_set_target_val(PWM4_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(0) | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1)); + clock_enable(CCGR_PWM4, true); + } else { + clock_enable(CCGR_PWM4, false); + } + return; + default: + printf("Invalid pwm index\n"); + return; + } +} + void init_uart_clk(u32 index) { /*