From patchwork Mon Feb 28 04:55:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hari Nagalla X-Patchwork-Id: 1598493 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=STYJziIN; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4K6SlT1YM5z9sGS for ; Mon, 28 Feb 2022 15:56:37 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 2FDDD83C58; Mon, 28 Feb 2022 05:56:21 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="STYJziIN"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 5856283A29; Mon, 28 Feb 2022 05:56:06 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id D9E2783BDE for ; Mon, 28 Feb 2022 05:55:57 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=hnagalla@ti.com Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 21S4tt2I098740 for ; Sun, 27 Feb 2022 22:55:55 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1646024155; bh=ddP+da43owOFzdSYiE78h9YbDVYSlcXTvmW1MhQRVWk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=STYJziINqMtPSM4rpotCelMM1Z8Zz3IPbVXceEM35wQrUjtE/TN29CrS4C2DPPPFq wIrihFCydLKN+oMPQ5lJhB0EUidvxxmNp0UW01RP6QVi8k0Fb90JYbBF9HX4ZBa8/H hFqGXngVTDNt97DhiNx5KeQ736I1OLpJjdFriNgk= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 21S4ttB1033905 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL) for ; Sun, 27 Feb 2022 22:55:55 -0600 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Sun, 27 Feb 2022 22:55:55 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Sun, 27 Feb 2022 22:55:55 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 21S4tt2K047639; Sun, 27 Feb 2022 22:55:55 -0600 From: Hari Nagalla To: CC: Subject: [PATCH v2 3/4] arch: arm: mach-k3: am642_init: Probe ESM nodes Date: Sun, 27 Feb 2022 22:55:53 -0600 Message-ID: <20220228045554.3048-4-hnagalla@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220228045554.3048-1-hnagalla@ti.com> References: <20220228045554.3048-1-hnagalla@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean On AM64x devices, it is possible to route Main ESM0 error events to MCU ESM. MCU ESM high error output can trigger the reset logic to reset the device. So, for these devices we expect two ESM device nodes in the device tree, one for Main ESM and the another MCU ESM in the device tree. When these ESM device nodes are properly configired it is possible to route the Main RTI0 WWDT output to the MCU ESM high ouput through Main ESM and trigger a device reset when CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RESET_EN_Z is set to '0'. On K3 AM64x devices, the R5 SPL u-boot handles the ESM device node configurations. Signed-off-by: Hari Nagalla Reviewed-by: Christian Gmeiner --- arch/arm/mach-k3/am642_init.c | 29 +++++++++++++++++++++++++---- 1 file changed, 25 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c index 543dea02bc..f171c1e254 100644 --- a/arch/arm/mach-k3/am642_init.c +++ b/arch/arm/mach-k3/am642_init.c @@ -24,12 +24,22 @@ #include #if defined(CONFIG_SPL_BUILD) +#define MCU_CTRL_MMR0_BASE 0x04500000 +#define CTRLMMR_MCU_RST_CTRL 0x04518170 static void ctrl_mmr_unlock(void) { /* Unlock all PADCFG_MMR1 module registers */ mmr_unlock(PADCFG_MMR1_BASE, 1); + /* Unlock all MCU_CTRL_MMR0 module registers */ + mmr_unlock(MCU_CTRL_MMR0_BASE, 0); + mmr_unlock(MCU_CTRL_MMR0_BASE, 1); + mmr_unlock(MCU_CTRL_MMR0_BASE, 2); + mmr_unlock(MCU_CTRL_MMR0_BASE, 3); + mmr_unlock(MCU_CTRL_MMR0_BASE, 4); + mmr_unlock(MCU_CTRL_MMR0_BASE, 6); + /* Unlock all CTRL_MMR0 module registers */ mmr_unlock(CTRL_MMR0_BASE, 0); mmr_unlock(CTRL_MMR0_BASE, 1); @@ -37,9 +47,6 @@ static void ctrl_mmr_unlock(void) mmr_unlock(CTRL_MMR0_BASE, 3); mmr_unlock(CTRL_MMR0_BASE, 5); mmr_unlock(CTRL_MMR0_BASE, 6); - - /* Unlock all MCU_PADCFG_MMR1 module registers */ - mmr_unlock(MCU_PADCFG_MMR1_BASE, 1); } /* @@ -144,7 +151,7 @@ int fdtdec_board_setup(const void *fdt_blob) void board_init_f(ulong dummy) { -#if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM64_DDRSS) +#if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM64_DDRSS) || defined(CONFIG_ESM_K3) struct udevice *dev; int ret; #endif @@ -194,6 +201,20 @@ void board_init_f(ulong dummy) /* Output System Firmware version info */ k3_sysfw_print_ver(); +#if defined(CONFIG_ESM_K3) + /* Probe/configure ESM0 */ + ret = uclass_get_device_by_name(UCLASS_MISC, "esm@420000", &dev); + if (ret) + printf("esm main init failed: %d\n", ret); + + /* Probe/configure MCUESM */ + ret = uclass_get_device_by_name(UCLASS_MISC, "esm@4100000", &dev); + if (ret) + printf("esm mcu init failed: %d\n", ret); + + enable_mcu_esm_reset(); +#endif + #if defined(CONFIG_K3_AM64_DDRSS) ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret)