From patchwork Thu Feb 10 16:25:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 1591226 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=rpALP2l+; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4Jvhts0Ddkz9s0r for ; Fri, 11 Feb 2022 03:25:39 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 2692B81A03; Thu, 10 Feb 2022 17:25:30 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="rpALP2l+"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id DB4FE81D5A; Thu, 10 Feb 2022 17:25:27 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 9779681A03 for ; Thu, 10 Feb 2022 17:25:24 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=kabel@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 23983B80816; Thu, 10 Feb 2022 16:25:24 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7ABB9C004E1; Thu, 10 Feb 2022 16:25:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1644510322; bh=5Eceo2x6UJB6gSI7rVnJI3o2UzQDKEBMqcRwFZrzT7w=; h=From:To:Cc:Subject:Date:From; b=rpALP2l+q6clIJgoofSus2+9FzRhwftW0trZzsa4tcYXrXK1p1FP8dOz4HkB3VzYJ ZSBzCL4SiMgafZU9hhyXx1PUFwwxrBYyg4khEGDt+g0fv9RwigTXOpVnbjNamUZe+G 8RQmGM1QWRMdyWhTj/D2El21L7CV1FJS2gJ6cW8U6GAJeQtyr5RYks0BWCgF8n9dAv PXaq67lGxiCVe8et8Ez/3ofL94Exp3mfrfYei1htwAAvfIQ8rP4bc7C4YArkOSAB3W dSZyZEfhRNA/3Jz8bXUWR8IiJzGKT/pB2phsHWEEFrVr8nhGRABNyNHORgvahMMn+v Aj2L5XMzVhTpA== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Chris Packham , Stefan Roese Cc: "u-boot@lists.denx.de" , Mario Six , Dennis Gilmore , =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH u-boot-marvell RFC] PLEASE TEST: ddr: marvell: a38x: fix BYTE_HOMOGENEOUS_SPLIT_OUT decision Date: Thu, 10 Feb 2022 17:25:17 +0100 Message-Id: <20220210162517.8485-1-kabel@kernel.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean From: Marek Behún In commit 3fc92a215b69 ("ddr: marvell: a38x: fix SPLIT_OUT_MIX state decision") I ported a cleaned up and changed version of patch mv_ddr: a380: fix SPLIT_OUT_MIX state decision In the port we removed checking for BYTE_HOMOGENEOUS_SPLIT_OUT bit, because: - the fix seemed to work without it - the bit was checked for only at one place out of two, while the second bit, BYTE_SPLIT_OUT_MIX, was checked for in both cases - without the removal it didn't work on Allied Telesis' x530 board We recently had a chance to test on more boards, and it seems that the change needs to be opposite: instead of removing the check for BYTE_HOMOGENEOUS_SPLIT_OUT from the first if() statement, the check needs to be added also to the second one - it needs to be at both places. With this change all the Turris Omnia boards I have had available to test seem to work, I didn't encounter not even one failed DDR training. As last time, I am noting that I do not understand what this code is actually doing, I haven't studied the DDR training algorithm and I suspect that no one will be able to explain it to U-Boot contributors, so we are left with this blind poking in the code with testing whether it works on several boards and hoping it doesn't break anything for anyone :-(. Signed-off-by: Marek Behún Tested-by: Chris Packham Reviewed-by: Stefan Roese --- drivers/ddr/marvell/a38x/ddr3_training_centralization.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/ddr/marvell/a38x/ddr3_training_centralization.c b/drivers/ddr/marvell/a38x/ddr3_training_centralization.c index 42308b6965..be9f985f22 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_centralization.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_centralization.c @@ -180,7 +180,8 @@ static int ddr3_tip_centralization(u32 dev_num, u32 mode) [bit_id], EDGE_1); if (current_byte_status & - BYTE_SPLIT_OUT_MIX) { + (BYTE_SPLIT_OUT_MIX | + BYTE_HOMOGENEOUS_SPLIT_OUT)) { if (cur_start_win[bit_id] >= 64) cur_start_win[bit_id] -= 64; else @@ -197,7 +198,8 @@ static int ddr3_tip_centralization(u32 dev_num, u32 mode) EDGE_1); if (cur_end_win[bit_id] >= 64 && (current_byte_status & - BYTE_SPLIT_OUT_MIX)) { + (BYTE_SPLIT_OUT_MIX | + BYTE_HOMOGENEOUS_SPLIT_OUT))) { cur_end_win[bit_id] -= 64; DEBUG_CENTRALIZATION_ENGINE (DEBUG_LEVEL_INFO,