@@ -25,6 +25,9 @@ config TARGET_P3041DS
select PHYS_64BIT
select ARCH_P3041
select BOARD_LATE_INIT if CHAIN_OF_TRUST
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
imply CMD_SATA
imply PANIC_HANG
@@ -33,6 +36,9 @@ config TARGET_P4080DS
select PHYS_64BIT
select ARCH_P4080
select BOARD_LATE_INIT if CHAIN_OF_TRUST
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
imply CMD_SATA
imply PANIC_HANG
@@ -41,6 +47,9 @@ config TARGET_P5040DS
select PHYS_64BIT
select ARCH_P5040
select BOARD_LATE_INIT if CHAIN_OF_TRUST
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
imply CMD_SATA
imply PANIC_HANG
@@ -102,6 +111,9 @@ config TARGET_P2041RDB
select ARCH_P2041
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select PHYS_64BIT
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
imply CMD_SATA
imply FSL_SATA
@@ -117,6 +129,9 @@ config TARGET_T1024RDB
select SUPPORT_SPL
select PHYS_64BIT
select FSL_DDR_INTERACTIVE
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
imply CMD_EEPROM
imply PANIC_HANG
@@ -126,6 +141,9 @@ config TARGET_T1042RDB
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
config TARGET_T1042D4RDB
bool "Support T1042D4RDB"
@@ -133,6 +151,9 @@ config TARGET_T1042D4RDB
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
imply PANIC_HANG
config TARGET_T1042RDB_PI
@@ -141,6 +162,9 @@ config TARGET_T1042RDB_PI
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
imply PANIC_HANG
config TARGET_T2080QDS
@@ -151,6 +175,9 @@ config TARGET_T2080QDS
select PHYS_64BIT
select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
select FSL_DDR_INTERACTIVE
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
imply CMD_SATA
config TARGET_T2080RDB
@@ -159,6 +186,9 @@ config TARGET_T2080RDB
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
imply CMD_SATA
imply PANIC_HANG
@@ -168,6 +198,9 @@ config TARGET_T4240RDB
select SUPPORT_SPL
select PHYS_64BIT
select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
imply CMD_SATA
imply PANIC_HANG
@@ -56,6 +56,7 @@
#ifdef CONFIG_U_QE
#include <fsl_qe.h>
#endif
+#include <dm.h>
#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
/*
@@ -974,8 +975,6 @@ int cpu_init_r(void)
#endif
#ifdef CONFIG_FSL_CAAM
- sec_init();
-
#if defined(CONFIG_ARCH_C29X)
if ((SVR_SOC_VER(svr) == SVR_C292) ||
(SVR_SOC_VER(svr) == SVR_C293))
@@ -1014,6 +1013,20 @@ int cpu_init_r(void)
return 0;
}
+#ifdef CONFIG_ARCH_MISC_INIT
+int arch_misc_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+
+ return 0;
+}
+#endif
+
void arch_preboot_os(void)
{
u32 msr;
new file mode 100644
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright 2021 NXP
+ *
+ * Gaurav Jain <gaurav.jain@nxp.com>
+ */
+
+#ifndef _U_BOOT_PPC_H_
+#define _U_BOOT_PPC_H_
+
+#ifndef __ASSEMBLY__
+
+int arch_misc_init(void);
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _U_BOOT_PPC_H_ */
@@ -21,5 +21,6 @@
/* Use the generic board which requires a unified bd_info */
#include <asm-generic/u-boot.h>
#include <asm/ppc.h>
+#include <asm/u-boot-ppc.h>
#endif /* __U_BOOT_H__ */
@@ -34,7 +34,6 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
-CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
@@ -32,7 +32,6 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
-CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
@@ -32,7 +32,6 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
-CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
@@ -32,7 +32,6 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
-CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
@@ -44,7 +44,6 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
-CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
@@ -35,7 +35,6 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
-CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
@@ -33,7 +33,6 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
-CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
@@ -38,7 +38,6 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
-CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133330000
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
@@ -39,7 +39,6 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
-CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133330000
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
@@ -30,7 +30,6 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
-CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133333333
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y