@@ -40,10 +40,11 @@ static int spartan2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
/* ------------------------------------------------------------------------- */
/* Spartan-II Generic Implementation */
-static int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize,
+static int spartan2_load(xilinx_desc **desc_ptr, const void *buf, size_t bsize,
bitstream_type bstype)
{
int ret_val = FPGA_FAIL;
+ xilinx_desc *desc = *desc_ptr;
switch (desc->iface) {
case slave_serial:
@@ -44,10 +44,11 @@ static int spartan3_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
/* ------------------------------------------------------------------------- */
/* Spartan-II Generic Implementation */
-static int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize,
+static int spartan3_load(xilinx_desc **desc_ptr, const void *buf, size_t bsize,
bitstream_type bstype)
{
int ret_val = FPGA_FAIL;
+ xilinx_desc *desc = *desc_ptr;
switch (desc->iface) {
case slave_serial:
@@ -26,7 +26,7 @@ static ulong versal_align_dma_buffer(ulong *buf, u32 len)
return (ulong)buf;
}
-static int versal_load(xilinx_desc *desc, const void *buf, size_t bsize,
+static int versal_load(xilinx_desc **desc_ptr, const void *buf, size_t bsize,
bitstream_type bstype)
{
ulong bin_buf;
@@ -93,10 +93,11 @@ static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize);
static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize);
static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
-static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize,
+static int virtex2_load(xilinx_desc **desc_ptr, const void *buf, size_t bsize,
bitstream_type bstype)
{
int ret_val = FPGA_FAIL;
+ xilinx_desc *desc = *desc_ptr;
switch (desc->iface) {
case slave_serial:
@@ -153,7 +153,7 @@ int xilinx_load(xilinx_desc **desc_ptr, const void *buf, size_t bsize,
return FPGA_FAIL;
}
- return desc->operations->load(desc, buf, bsize, bstype);
+ return desc->operations->load(desc_ptr, buf, bsize, bstype);
}
#if defined(CONFIG_CMD_FPGA_LOADFS)
@@ -199,8 +199,8 @@ static int zynqmp_validate_bitstream(xilinx_desc *desc, const void *buf,
return 0;
}
-static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize,
- bitstream_type bstype)
+static int zynqmp_load(xilinx_desc **desc_ptr, const void *buf, size_t bsize,
+ bitstream_type bstype)
{
ALLOC_CACHE_ALIGN_BUFFER(u32, bsizeptr, 1);
u32 swap = 0;
@@ -209,6 +209,7 @@ static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize,
u32 buf_lo, buf_hi;
u32 ret_payload[PAYLOAD_ARG_CNT];
bool xilfpga_old = false;
+ xilinx_desc *desc = *desc_ptr;
if (zynqmp_firmware_version() <= PMUFW_V1_0) {
puts("WARN: PMUFW v1.0 or less is detected\n");
@@ -370,11 +370,12 @@ static int zynq_validate_bitstream(xilinx_desc *desc, const void *buf,
return 0;
}
-static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize,
+static int zynq_load(xilinx_desc **desc_ptr, const void *buf, size_t bsize,
bitstream_type bstype)
{
unsigned long ts; /* Timestamp */
u32 isr_status, swap;
+ xilinx_desc *desc = *desc_ptr;
/*
* send bsize inplace of blocksize as it was not a bitstream
@@ -48,7 +48,7 @@ typedef struct { /* typedef xilinx_desc */
} xilinx_desc; /* end, typedef xilinx_desc */
struct xilinx_fpga_op {
- int (*load)(xilinx_desc *desc, const void *buf, size_t bsize,
+ int (*load)(xilinx_desc **desc_ptr, const void *buf, size_t bsize,
bitstream_type bstype);
int (*loadfs)(xilinx_desc *desc, const void *buf, size_t bsize,
fpga_fs_info *fpga_fsinfo);