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Tue, 7 Dec 2021 07:42:21 +0000 From: Gaurav Jain To: u-boot@lists.denx.de Cc: Stefano Babic , Fabio Estevam , Peng Fan , Simon Glass , Priyanka Jain , Ye Li , Horia Geanta , Ji Luo , Franck Lenormand , Silvano Di Ninno , Sahil malhotra , Pankaj Gupta , Varun Sethi , "NXP i . MX U-Boot Team" , Shengzhou Liu , Mingkai Hu , Rajesh Bhagat , Meenakshi Aggarwal , Wasim Khan , Alison Wang , Pramod Kumar , Tang Yuantian , Adrian Alonso , Vladimir Oltean , Gaurav Jain Subject: [PATCH v7 03/15] crypto/fsl: i.MX8M: Enable Job ring driver model in SPL and U-Boot. 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Signed-off-by: Gaurav Jain Reviewed-by: Ye Li --- arch/arm/Kconfig | 2 +- arch/arm/include/asm/arch-imx8m/imx-regs.h | 1 + arch/arm/mach-imx/imx8m/Kconfig | 18 ++++++++++++++++++ arch/arm/mach-imx/imx8m/soc.c | 10 +++++++++- board/freescale/imx8mm_evk/spl.c | 9 ++++++++- board/freescale/imx8mn_evk/spl.c | 8 ++++++-- board/freescale/imx8mp_evk/spl.c | 13 +++++++++++-- board/freescale/imx8mq_evk/spl.c | 9 +++++++-- drivers/crypto/fsl/jr.c | 14 +++++++++++--- scripts/config_whitelist.txt | 1 + 10 files changed, 73 insertions(+), 12 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f7f03837fe..550f884077 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -815,7 +815,7 @@ config ARCH_IMX8M select ARM64 select GPIO_EXTRA_HEADER select MACH_IMX - select SYS_FSL_HAS_SEC if IMX_HAB + select SYS_FSL_HAS_SEC select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE select SYS_I2C_MXC diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index b800da13a1..ff8de53f67 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -72,6 +72,7 @@ #define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \ CONFIG_SYS_FSL_SEC_OFFSET) #define CONFIG_SYS_FSL_JR0_OFFSET (0x1000) +#define CONFIG_SYS_FSL_JR1_OFFSET (0x2000) #define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \ CONFIG_SYS_FSL_JR0_OFFSET) #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 276b8bd974..a9acf6474f 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -38,6 +38,10 @@ config TARGET_IMX8MQ_EVK bool "imx8mq_evk" select IMX8MQ select IMX8M_LPDDR4 + select FSL_CAAM + select MISC + select ARCH_MISC_INIT + select SPL_CRYPTO if SPL config TARGET_IMX8MQ_PHANBELL bool "imx8mq_phanbell" @@ -50,6 +54,10 @@ config TARGET_IMX8MM_EVK select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 + select FSL_CAAM + select MISC + select ARCH_MISC_INIT + select SPL_CRYPTO if SPL config TARGET_IMX8MM_ICORE_MX8MM bool "Engicam i.Core MX8M Mini SOM" @@ -88,6 +96,9 @@ config TARGET_IMX8MN_EVK select IMX8MN select SUPPORT_SPL select IMX8M_LPDDR4 + select FSL_CAAM + select MISC + select SPL_CRYPTO if SPL config TARGET_IMX8MN_DDR4_EVK bool "imx8mn DDR4 EVK board" @@ -95,6 +106,9 @@ config TARGET_IMX8MN_DDR4_EVK select IMX8MN select SUPPORT_SPL select IMX8M_DDR4 + select FSL_CAAM + select MISC + select SPL_CRYPTO if SPL config TARGET_IMX8MP_EVK bool "imx8mp LPDDR4 EVK board" @@ -102,6 +116,10 @@ config TARGET_IMX8MP_EVK select IMX8MP select SUPPORT_SPL select IMX8M_LPDDR4 + select FSL_CAAM + select MISC + select ARCH_MISC_INIT + select SPL_CRYPTO if SPL config TARGET_PICO_IMX8MQ bool "Support Technexion Pico iMX8MQ" diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 863508776d..0f9bd77354 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2017-2019 NXP + * Copyright 2017-2019, 2021 NXP * * Peng Fan */ @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -1197,6 +1198,13 @@ static void acquire_buildinfo(void) int arch_misc_init(void) { + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev); + if (ret) + printf("Failed to initialize %s: %d\n", dev->name, ret); + acquire_buildinfo(); return 0; diff --git a/board/freescale/imx8mm_evk/spl.c b/board/freescale/imx8mm_evk/spl.c index 4ef7f6f180..c81128f442 100644 --- a/board/freescale/imx8mm_evk/spl.c +++ b/board/freescale/imx8mm_evk/spl.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2019 NXP + * Copyright 2019, 2021 NXP */ #include @@ -51,6 +51,13 @@ static void spl_dram_init(void) void spl_board_init(void) { + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev); + if (ret) + printf("Failed to initialize %s: %d\n", dev->name, ret); + puts("Normal Boot\n"); } diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freescale/imx8mn_evk/spl.c index 03f2a56e80..ab19dabf7b 100644 --- a/board/freescale/imx8mn_evk/spl.c +++ b/board/freescale/imx8mn_evk/spl.c @@ -1,7 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* - * Copyright 2018-2019 NXP + * Copyright 2018-2019, 2021 NXP * - * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -49,6 +49,10 @@ void spl_board_init(void) struct udevice *dev; int ret; + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev); + if (ret) + printf("Failed to initialize %s: %d\n", dev->name, ret); + puts("Normal Boot\n"); ret = uclass_get_device_by_name(UCLASS_CLK, diff --git a/board/freescale/imx8mp_evk/spl.c b/board/freescale/imx8mp_evk/spl.c index eca42c756e..bcef96caa3 100644 --- a/board/freescale/imx8mp_evk/spl.c +++ b/board/freescale/imx8mp_evk/spl.c @@ -1,7 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* - * Copyright 2018-2019 NXP + * Copyright 2018-2019, 2021 NXP * - * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -20,6 +20,8 @@ #include #include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -35,6 +37,13 @@ void spl_dram_init(void) void spl_board_init(void) { + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev); + if (ret) + printf("Failed to initialize %s: %d\n", dev->name, ret); + /* * Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does * not allow to change it. Should set the clock after PMIC diff --git a/board/freescale/imx8mq_evk/spl.c b/board/freescale/imx8mq_evk/spl.c index 67d069b2b0..8a47dd01a5 100644 --- a/board/freescale/imx8mq_evk/spl.c +++ b/board/freescale/imx8mq_evk/spl.c @@ -1,8 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2018 NXP + * Copyright 2018, 2021 NXP * - * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -22,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -199,6 +199,11 @@ int power_init_board(void) void spl_board_init(void) { +#ifdef CONFIG_FSL_CAAM + if (sec_init()) + printf("\nsec_init failed!\n"); + +#endif puts("Normal Boot\n"); } diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index 441550f348..9379b86955 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -43,9 +43,17 @@ struct udevice *caam_dev; #define SEC_ADDR(idx) \ (ulong)((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx])) -#define SEC_JR0_ADDR(idx) \ +#ifndef CONFIG_IMX8M +#define SEC_JR_ADDR(idx) \ (ulong)(SEC_ADDR(idx) + \ (CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET)) +#define JR_ID 0 +#else +#define SEC_JR_ADDR(idx) \ + (ulong)(SEC_ADDR(idx) + \ + (CONFIG_SYS_FSL_JR1_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET)) +#define JR_ID 1 +#endif struct caam_regs caam_st; #endif @@ -669,8 +677,8 @@ int sec_init_idx(uint8_t sec_idx) caam = dev_get_priv(caam_dev); #else caam_st.sec = (void *)SEC_ADDR(sec_idx); - caam_st.regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx); - caam_st.jrid = 0; + caam_st.regs = (struct jr_regs *)SEC_JR_ADDR(sec_idx); + caam_st.jrid = JR_ID; caam = &caam_st; #endif ccsr_sec_t *sec = caam->sec; diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index b9c1c61e13..81de1a3793 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1848,6 +1848,7 @@ CONFIG_SYS_FSL_IFC_SIZE2 CONFIG_SYS_FSL_ISBC_VER CONFIG_SYS_FSL_JR0_ADDR CONFIG_SYS_FSL_JR0_OFFSET +CONFIG_SYS_FSL_JR1_OFFSET CONFIG_SYS_FSL_LS1_CLK_ADDR CONFIG_SYS_FSL_LSCH3_SERDES_ADDR CONFIG_SYS_FSL_MAX_NUM_OF_SEC