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[68.175.35.150]) by smtp.gmail.com with ESMTPSA id o1sm395201qtw.1.2021.11.24.11.40.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Nov 2021 11:40:25 -0800 (PST) From: Jim Posen To: u-boot@lists.denx.de Cc: trini@konsulko.com, mbrugger@suse.com, Jim Posen Subject: [PATCH v2 2/6] Hypervisor mode interrupt vector table Date: Wed, 24 Nov 2021 14:39:57 -0500 Message-Id: <20211124194001.443232-3-jim.posen@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211124194001.443232-1-jim.posen@gmail.com> References: <20211124194001.443232-1-jim.posen@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.37 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Create separate vector table for exceptions taken to PL2, which happens when U-Boot is running in hypervisor mode. The handler logic is different enough that a separate vector table is the simplest way to handle it. Signed-off-by: Jim Posen --- (no changes since v1) arch/arm/lib/vectors.S | 95 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 95 insertions(+) diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S index 56f3681558..89b91b27da 100644 --- a/arch/arm/lib/vectors.S +++ b/arch/arm/lib/vectors.S @@ -117,6 +117,39 @@ _not_used: .word not_used _irq: .word irq _fiq: .word fiq +#ifdef CONFIG_CPU_V7_HAS_VIRT +/* + ************************************************************************* + * + * Hypervisor mode interrupt vectors table + * + ************************************************************************* + */ + + .globl hyp_vector_table + + .align 5 +hyp_vector_table: + ldr pc, _hyp_reset + ldr pc, _hyp_undefined_instruction + ldr pc, _hyp_software_interrupt + ldr pc, _hyp_prefetch_abort + ldr pc, _hyp_data_abort + ldr pc, _hyp_not_used + ldr pc, _hyp_irq + ldr pc, _hyp_fiq + +_hyp_reset: .word reset +_hyp_undefined_instruction: .word hyp_undefined_instruction +_hyp_software_interrupt: .word hyp_software_interrupt +_hyp_prefetch_abort: .word hyp_prefetch_abort +_hyp_data_abort: .word hyp_data_abort +_hyp_not_used: .word hyp_not_used +_hyp_irq: .word hyp_irq +_hyp_fiq: .word hyp_fiq + +#endif /* CONFIG_CPU_V7_HAS_VIR + .balignl 16,0xdeadbeef /* @@ -139,6 +172,15 @@ data_abort: not_used: irq: fiq: +#ifdef CONFIG_CPU_V7_HAS_VIRT +hyp_undefined_instruction: +hyp_software_interrupt: +hyp_prefetch_abort: +hyp_data_abort: +hyp_not_used: +hyp_irq: +hyp_fiq: +#endif /* CONFIG_CPU_V7_HAS_VIRT 1: b 1b /* hang and never return */ @@ -289,4 +331,57 @@ fiq: bad_save_user_regs bl do_fiq +#ifdef CONFIG_CPU_V7_HAS_VIRT + +/** + * Hypervisor mode exception handlers + * + * If exception is taken to EL2, U-Boot must have been running in hypervisor + * mode. Use the existing stack to save register values onto because + * overwriting the stack pointer would leave no way to inspect its value. + */ + + .macro hyp_enter_exception + str sp, [sp, #(-S_FRAME_SIZE + S_SP)] + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} + mrs r1, elr_hyp + mrs r2, spsr + str lr, [sp, #S_LR] + str r1, [sp, #S_PC] + str r2, [sp, #S_PSR] + str r0, [sp, #S_OLD_R0] + mov r0, sp + .endm + +hyp_undefined_instruction: + hyp_enter_exception + bl do_undefined_instruction + +hyp_software_interrupt: + hyp_enter_exception + bl do_software_interrupt + +hyp_prefetch_abort: + hyp_enter_exception + bl do_prefetch_abort + +hyp_data_abort: + hyp_enter_exception + bl do_data_abort + +hyp_not_used: + hyp_enter_exception + bl do_not_used + +hyp_irq: + hyp_enter_exception + bl do_irq + +hyp_fiq: + hyp_enter_exception + bl do_fiq + +#endif /* CONFIG_CPU_V7_HAS_VIRT */ + #endif /* CONFIG_SPL_BUILD */