From patchwork Wed Oct 13 13:48:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Jorge Ramirez-Ortiz, Foundries" X-Patchwork-Id: 1540423 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=foundries.io header.i=@foundries.io header.a=rsa-sha256 header.s=google header.b=CCLNRSNN; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (unknown [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4HTv4w5DbCz9sR4 for ; Thu, 14 Oct 2021 00:48:28 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 51D2F8291E; Wed, 13 Oct 2021 15:48:13 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=foundries.io Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=foundries.io header.i=@foundries.io header.b="CCLNRSNN"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 9A8B283172; Wed, 13 Oct 2021 15:48:11 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 8DD8181725 for ; Wed, 13 Oct 2021 15:48:08 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=foundries.io Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=jorge@foundries.io Received: by mail-wr1-x42f.google.com with SMTP id r18so8643358wrg.6 for ; Wed, 13 Oct 2021 06:48:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foundries.io; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=EGwgdastXo8ieiS3Ao06sWMhM3uxHXv/nnE3xn8LAWQ=; b=CCLNRSNNtDptbejdrW5dWLIIo/o9cH3imEzkk8AweOIECixCsFZBO4A0Eesh0FV4di 0jBg/5jnqyjhiCs/L94UgJTI+8yL86/wTIJl+7HESIu8WXMFSsNMwBxvxHdgFwd4Uz1G NuiKcNDb5WNI0/B2LEgw378enAwTjL8v6KZmjRYJ2wL+UTQ/VpN72yEedm+Qe4MoRbHl BwK2K4arn2B6pVbBBfMpRZjgT7W0dJAHCLkY6q6wjxTvBBJt96FxaZ7GMG0BMBJjmPMV bnPQf2jZEKmd6xLPWaALRR82Md7B9vAdPXixJgghNwNqM9w51jKRYh2iFlz1cR8/b/0h eIXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=EGwgdastXo8ieiS3Ao06sWMhM3uxHXv/nnE3xn8LAWQ=; b=qI5q3CkfAbMJz3mg7hrYqrcqzums+W3nt1ecMA2XbYsXhaCZQCmxw3dUB9uprG/ApS iGgvAzrIHTYC3cBA0rXfNco+PA56P+o6w32oXkZDmsUAbKlXt49jqllyIDg7lGa9YPz0 iUqdAJvRsZGmAazSLXRPg1L8tFQxR1uyTBxnhMpQ0PRzQoSYOrm4zgUl4d6xm0CkAlWm YOmC0V8E6HzEQ7HZK7Ojom/T3jJyihDuZckTF6ezneulz45vrCg8IjY7x3cBrESnjJX4 k3fS/9+n4L7RCNc4RV4KGnv81snPp1J8wDnbVJtRXqRw5raGOLWTQeHnxJn/i3hmupgp Z40g== X-Gm-Message-State: AOAM53011pdZXdBwLNcTXi3GEuCwDobnWOE81lW6BvwzZTkZw7N8zExB Gj0JVAMrUJppFS3QwMDvX+vJz0bRKeNh0Q== X-Google-Smtp-Source: ABdhPJx4kU9tppbn/GpTY2f0H1hIJJ7Kdqywenu/C4NChvzlfiYfqt8bZsnCA8+Dj/MTun6VSqPe3g== X-Received: by 2002:a5d:4b85:: with SMTP id b5mr41272083wrt.362.1634132888178; Wed, 13 Oct 2021 06:48:08 -0700 (PDT) Received: from localhost.localdomain (60.red-83-35-113.dynamicip.rima-tde.net. [83.35.113.60]) by smtp.gmail.com with ESMTPSA id j11sm5359135wmi.24.2021.10.13.06.48.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Oct 2021 06:48:07 -0700 (PDT) From: Jorge Ramirez-Ortiz To: jorge@foundries.io, michal.simek@xilinx.com Cc: u-boot@lists.denx.de, igor.opaniuk@foundries.io Subject: [PATCHv3] zynqmp: restore the jtag interface Date: Wed, 13 Oct 2021 15:48:00 +0200 Message-Id: <20211013134800.19452-1-jorge@foundries.io> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean When boot.bin is configured for secure boot the CSU will disable the JTAG interface on all cases. Some boards might rely on this interface for flashing to QSPI in which case those systems might end up bricked during development. This commit will restore the interface under CSU control Signed-off-by: Jorge Ramirez-Ortiz --- v3: delete unvalid removal of empty line arch/arm/mach-zynqmp/Kconfig | 8 +++++ arch/arm/mach-zynqmp/include/mach/hardware.h | 31 +++++++++++++++----- board/xilinx/zynqmp/zynqmp.c | 19 ++++++++++++ 3 files changed, 51 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig index f7b08db355..ee0895d9a2 100644 --- a/arch/arm/mach-zynqmp/Kconfig +++ b/arch/arm/mach-zynqmp/Kconfig @@ -149,6 +149,14 @@ config SPL_ZYNQMP_ALT_BOOTMODE_ENABLED Overwrite bootmode selected via boot mode pins to tell SPL what should be the next boot device. +config SPL_ZYNQMP_RESTORE_JTAG + bool "Restore JTAG" + depends on SPL + help + Booting SPL in secure mode causes the CSU to disable the JTAG interface + even if no eFuses were burnt. This option restores the interface if + possible. + config ZYNQ_SDHCI_MAX_FREQ default 200000000 diff --git a/arch/arm/mach-zynqmp/include/mach/hardware.h b/arch/arm/mach-zynqmp/include/mach/hardware.h index eebf38551c..e6a3ee4a57 100644 --- a/arch/arm/mach-zynqmp/include/mach/hardware.h +++ b/arch/arm/mach-zynqmp/include/mach/hardware.h @@ -39,20 +39,26 @@ #define RESET_REASON_INTERNAL BIT(1) #define RESET_REASON_EXTERNAL BIT(0) +#define CRLAPB_DBG_LPD_CTRL_SETUP_CLK 0x01002002 +#define CRLAPB_RST_LPD_DBG_RESET 0 + struct crlapb_regs { u32 reserved0[36]; u32 cpu_r5_ctrl; /* 0x90 */ - u32 reserved1[37]; + u32 reserved1[7]; + u32 dbg_lpd_ctrl; /* 0xB0 */ + u32 reserved2[29]; u32 timestamp_ref_ctrl; /* 0x128 */ - u32 reserved2[53]; + u32 reserved3[53]; u32 boot_mode; /* 0x200 */ - u32 reserved3_0[7]; + u32 reserved4_0[7]; u32 reset_reason; /* 0x220 */ - u32 reserved3_1[6]; + u32 reserved4_1[6]; u32 rst_lpd_top; /* 0x23C */ - u32 reserved4[4]; + u32 rst_lpd_dbg; /* 0x240 */ + u32 reserved5[3]; u32 boot_pin_ctrl; /* 0x250 */ - u32 reserved5[21]; + u32 reserved6[21]; }; #define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR) @@ -141,12 +147,23 @@ struct apu_regs { #define ZYNQMP_SILICON_VER_MASK 0xF #define ZYNQMP_SILICON_VER_SHIFT 0 +#define CSU_JTAG_SEC_GATE_DISABLE GENMASK(7, 0) +#define CSU_JTAG_DAP_ENABLE_DEBUG GENMASK(7, 0) +#define CSU_JTAG_CHAIN_WR_SETUP GENMASK(1, 0) +#define CSU_PCAP_PROG_RELEASE_PL BIT(0) + struct csu_regs { u32 reserved0[4]; u32 multi_boot; - u32 reserved1[11]; + u32 reserved1[7]; + u32 jtag_chain_status_wr; + u32 jtag_chain_status; + u32 jtag_sec; + u32 jtag_dap_cfg; u32 idcode; u32 version; + u32 reserved2[3055]; + u32 pcap_prog; }; #define csu_base ((struct csu_regs *)ZYNQMP_CSU_BASEADDR) diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 000a7cde8d..b24db5306a 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -358,6 +358,21 @@ static int multi_boot(void) return multiboot; } +#if defined(CONFIG_SPL_BUILD) +static void restore_jtag(void) +{ + if (current_el() != 3) + return; + + writel(CSU_JTAG_SEC_GATE_DISABLE, &csu_base->jtag_sec); + writel(CSU_JTAG_DAP_ENABLE_DEBUG, &csu_base->jtag_dap_cfg); + writel(CSU_JTAG_CHAIN_WR_SETUP, &csu_base->jtag_chain_status_wr); + writel(CRLAPB_DBG_LPD_CTRL_SETUP_CLK, &crlapb_base->dbg_lpd_ctrl); + writel(CRLAPB_RST_LPD_DBG_RESET, &crlapb_base->rst_lpd_dbg); + writel(CSU_PCAP_PROG_RELEASE_PL, &csu_base->pcap_prog); +} +#endif + #define PS_SYSMON_ANALOG_BUS_VAL 0x3210 #define PS_SYSMON_ANALOG_BUS_REG 0xFFA50914 @@ -377,6 +392,10 @@ int board_init(void) zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj, zynqmp_pm_cfg_obj_size); printf("Silicon version:\t%d\n", zynqmp_get_silicon_version()); + + /* the CSU disables the JTAG interface when secure boot is enabled */ + if (CONFIG_IS_ENABLED(SPL_ZYNQMP_RESTORE_JTAG)) + restore_jtag(); #else if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM)) xilinx_read_eeprom();