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Fri, 17 Sep 2021 02:46:23 -0400 (EDT) From: Mathew McBride To: u-boot@lists.denx.de Cc: Mathew McBride Subject: [PATCH 4/4] rtc: rx8025: revise single register write to use offset Date: Fri, 17 Sep 2021 06:46:04 +0000 Message-Id: <20210917064604.3912-5-matt@traverse.com.au> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210917064604.3912-1-matt@traverse.com.au> References: <20210917064604.3912-1-matt@traverse.com.au> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Writing of individual registers was not functioning correctly as a 0 'offset' byte under DM-managed I2C was being appended in front of register we wanted to access. Signed-off-by: Mathew McBride --- drivers/rtc/rx8025.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/rtc/rx8025.c b/drivers/rtc/rx8025.c index 9423a1bb82..1394c2306a 100644 --- a/drivers/rtc/rx8025.c +++ b/drivers/rtc/rx8025.c @@ -214,11 +214,14 @@ static int rx8025_rtc_reset(struct udevice *dev) */ static int rtc_write(struct udevice *dev, uchar reg, uchar val) { - uchar buf[2]; - buf[0] = reg << 4; - buf[1] = val; + /* The RX8025/RX8035 uses the top 4 bits of the + * 'offset' byte as the start register address, + * and the bottom 4 bits as a 'transfer' mode setting + * (only applicable for reads) + */ + u8 offset = (reg << 4); - if (dm_i2c_write(dev, 0, buf, 2)) { + if (dm_i2c_reg_write(dev, offset, val)) { printf("Error writing to RTC\n"); return -EIO; }