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[PULL] u-boot-riscv/master

Message ID 20210706160205.GA11927@andestech.com
State Accepted
Delegated to: Tom Rini
Headers show
Series [PULL] u-boot-riscv/master | expand

Pull-request

git@source.denx.de:u-boot/custodians/u-boot-riscv.git

Message

Leo Liang July 6, 2021, 4:02 p.m. UTC 
Hi Tom,

The following changes since commit 1311dd37ecf476be041d0452d4ee38619aadd5de:

  Merge branch '2021-07-01-update-CI-containers' (2021-07-05 15:29:44 -0400)

are available in the Git repository at:

  git@source.denx.de:u-boot/custodians/u-boot-riscv.git 

for you to fetch changes up to 4b4159d0f31ca3e0174ccfdce9a24a1fe3671829:

  board: sifive: support spl multi-dtb on unmatched board (2021-07-06 20:24:26 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/8081

----------------------------------------------------------------
Dimitri John Ledkov (1):
      riscv: sifive: Set default fdtfile names

Green Wan (1):
      drivers: clk: sifive: fu740-prci: replace 'pciaux' with 'pcieaux'

Tianrui Wei (2):
      board: riscv: add openpiton-riscv64 SoC support
      mmc: openpiton: add piton_mmc driver

Zong Li (6):
      board: sifive: unmatched: add initial support for a platform ID EEPROM
      riscv: sifive: fu740: kconfig: Enable support for Opencores I2C controller
      riscv: sifive: fu740: Support i2c in spl
      board: sifive: Add an interface to get PCB revision
      riscv: dts: add dts for unmatched rev1
      board: sifive: support spl multi-dtb on unmatched board

 arch/riscv/Kconfig                                 |    4 +
 arch/riscv/cpu/fu740/Kconfig                       |    3 +
 arch/riscv/dts/Makefile                            |    3 +-
 arch/riscv/dts/fu740-c000-u-boot.dtsi              |    4 +
 .../dts/fu740-hifive-unmatched-a00-ddr-rev1.dtsi   | 1489 ++++++++++++++++++++
 .../dts/hifive-unmatched-a00-rev1-u-boot.dtsi      |    7 +
 arch/riscv/dts/hifive-unmatched-a00-rev1.dts       |    4 +
 arch/riscv/dts/openpiton-riscv64.dts               |  153 ++
 arch/riscv/include/asm/arch-fu740/eeprom.h         |   15 +
 board/openpiton/riscv64/Kconfig                    |   40 +
 board/openpiton/riscv64/MAINTAINERS                |    8 +
 board/openpiton/riscv64/Makefile                   |    5 +
 board/openpiton/riscv64/openpiton-riscv64.c        |   33 +
 board/sifive/unmatched/Kconfig                     |    1 +
 board/sifive/unmatched/Makefile                    |    1 +
 .../sifive/unmatched/hifive-platform-i2c-eeprom.c  |  574 ++++++++
 board/sifive/unmatched/spl.c                       |   28 +-
 configs/openpiton_riscv64_defconfig                |   76 +
 configs/openpiton_riscv64_spl_defconfig            |   87 ++
 configs/sifive_unleashed_defconfig                 |    1 +
 configs/sifive_unmatched_defconfig                 |    5 +
 doc/board/index.rst                                |    1 +
 doc/board/openpiton/index.rst                      |    9 +
 doc/board/openpiton/riscv64.rst                    |  376 +++++
 drivers/clk/sifive/fu740-prci.c                    |    6 +-
 drivers/mmc/Kconfig                                |    9 +
 drivers/mmc/Makefile                               |    1 +
 drivers/mmc/piton_mmc.c                            |  161 +++
 include/configs/openpiton-riscv64.h                |   61 +
 include/configs/sifive-unleashed.h                 |    1 +
 include/configs/sifive-unmatched.h                 |    7 +
 31 files changed, 3167 insertions(+), 6 deletions(-)
 create mode 100644 arch/riscv/dts/fu740-hifive-unmatched-a00-ddr-rev1.dtsi
 create mode 100644 arch/riscv/dts/hifive-unmatched-a00-rev1-u-boot.dtsi
 create mode 100644 arch/riscv/dts/hifive-unmatched-a00-rev1.dts
 create mode 100644 arch/riscv/dts/openpiton-riscv64.dts
 create mode 100644 arch/riscv/include/asm/arch-fu740/eeprom.h
 create mode 100644 board/openpiton/riscv64/Kconfig
 create mode 100644 board/openpiton/riscv64/MAINTAINERS
 create mode 100644 board/openpiton/riscv64/Makefile
 create mode 100644 board/openpiton/riscv64/openpiton-riscv64.c
 create mode 100644 board/sifive/unmatched/hifive-platform-i2c-eeprom.c
 create mode 100644 configs/openpiton_riscv64_defconfig
 create mode 100644 configs/openpiton_riscv64_spl_defconfig
 create mode 100644 doc/board/openpiton/index.rst
 create mode 100644 doc/board/openpiton/riscv64.rst
 create mode 100644 drivers/mmc/piton_mmc.c
 create mode 100644 include/configs/openpiton-riscv64.h

 Best regards,
 Leo

Comments

Tom Rini July 6, 2021, 7:52 p.m. UTC | #1 
On Wed, Jul 07, 2021 at 12:02:05AM +0800, Leo Liang wrote:

> Hi Tom,
> 
> The following changes since commit 1311dd37ecf476be041d0452d4ee38619aadd5de:
> 
>   Merge branch '2021-07-01-update-CI-containers' (2021-07-05 15:29:44 -0400)
> 
> are available in the Git repository at:
> 
>   git@source.denx.de:u-boot/custodians/u-boot-riscv.git 
> 
> for you to fetch changes up to 4b4159d0f31ca3e0174ccfdce9a24a1fe3671829:
> 
>   board: sifive: support spl multi-dtb on unmatched board (2021-07-06 20:24:26 +0800)
> 
> CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/8081
> 

Please note:
w+(openpiton_riscv64 openpiton_riscv64_spl) arch/riscv/dts/openpiton-riscv64.dtb: Warning (ranges_format): /soc:ranges: empty "ranges" property but its #address-cells (1) differs from / (2)
w+(openpiton_riscv64 openpiton_riscv64_spl) arch/riscv/dts/openpiton-riscv64.dtb: Warning (ranges_format): /soc:ranges: empty "ranges" property but its #size-cells (1) differs from / (2)

need to be fixed in a follow up PR (and the relevant dts files should be
added to the board MAINTAINER file too).  That said, applied to
u-boot/master, thanks!
Tianrui Wei July 7, 2021, 4:05 a.m. UTC | #2 
Hi Tom, Leo,

Apologies for making that mistake, and many many thanks for merging our patches! We’ve already fixed the problem with another patch.

Many thanks,
Tianrui

-----Original Message-----
From: Tom Rini <trini@konsulko.com>
Date: Wednesday, July 7, 2021 at 3:52 AM
To: Leo Liang <ycliang@andestech.com>
Cc: u-boot@lists.denx.de <u-boot@lists.denx.de>, rick@andestech.com <rick@andestech.com>, Tianrui Wei <tianrui-wei@outlook.com>
Subject: Re: [PULL] u-boot-riscv/master
On Wed, Jul 07, 2021 at 12:02:05AM +0800, Leo Liang wrote:

> Hi Tom,
>
> The following changes since commit 1311dd37ecf476be041d0452d4ee38619aadd5de:
>
>   Merge branch '2021-07-01-update-CI-containers' (2021-07-05 15:29:44 -0400)
>
> are available in the Git repository at:
>
>   git@source.denx.de<mailto:git@source.denx.de>:u-boot/custodians/u-boot-riscv.git
>
> for you to fetch changes up to 4b4159d0f31ca3e0174ccfdce9a24a1fe3671829:
>
>   board: sifive: support spl multi-dtb on unmatched board (2021-07-06 20:24:26 +0800)
>
> CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/8081
>

Please note:
w+(openpiton_riscv64 openpiton_riscv64_spl) arch/riscv/dts/openpiton-riscv64.dtb: Warning (ranges_format): /soc:ranges: empty "ranges" property but its #address-cells (1) differs from / (2)
w+(openpiton_riscv64 openpiton_riscv64_spl) arch/riscv/dts/openpiton-riscv64.dtb: Warning (ranges_format): /soc:ranges: empty "ranges" property but its #size-cells (1) differs from / (2)

need to be fixed in a follow up PR (and the relevant dts files should be
added to the board MAINTAINER file too).  That said, applied to
u-boot/master, thanks!

--
Tom