@@ -20,6 +20,8 @@
#include <linux/sizes.h>
#include "cadence_qspi.h"
+#define NSEC_PER_SEC 1000000000L
+
#define CQSPI_STIG_READ 0
#define CQSPI_STIG_WRITE 1
#define CQSPI_READ 2
@@ -208,6 +210,8 @@ static int cadence_spi_probe(struct udevice *bus)
priv->qspi_is_init = 1;
}
+ plat->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, plat->ref_clk_hz);
+
return 0;
}
@@ -27,6 +27,7 @@ struct cadence_spi_plat {
fdt_addr_t ahbsize;
bool use_dac_mode;
int read_delay;
+ u32 wr_delay;
/* Flash parameters */
u32 page_size;
@@ -730,6 +730,12 @@ cadence_qspi_apb_indirect_write_execute(struct cadence_spi_plat *plat,
writel(CQSPI_REG_INDIRECTWR_START,
plat->regbase + CQSPI_REG_INDIRECTWR);
+ /*
+ * Some delay is required for the above bit to be internally
+ * synchronized by the QSPI module.
+ */
+ ndelay(plat->wr_delay);
+
while (remaining > 0) {
write_bytes = remaining > page_size ? page_size : remaining;
writesl(plat->ahbbase, bb_txbuf, write_bytes >> 2);
Once the start bit is toggled it takes a small amount of time before it is internally synchronized. This means we can't start writing during that part. So add a small delay to allow the bit to be synchronized. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> --- drivers/spi/cadence_qspi.c | 4 ++++ drivers/spi/cadence_qspi.h | 1 + drivers/spi/cadence_qspi_apb.c | 6 ++++++ 3 files changed, 11 insertions(+)