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[v10,20/27] mtd: spi-nor-core: Do not make invalid quad enable fatal

Message ID 20210625191729.31798-21-p.yadav@ti.com
State Accepted
Commit b058f108d7d91f9a5f47c1d0d3ddf4e6ae030440
Delegated to: Jagannadha Sutradharudu Teki
Headers show
Series mtd: spi-nor-core: add xSPI Octal DTR support | expand

Commit Message

Pratyush Yadav June 25, 2021, 7:17 p.m. UTC 
The Micron MT35XU512ABA flash does not support the quad enable bit. But
instead of programming the Quad Enable Require field to 000b ("Device
does not have a QE bit"), it is programmed to 111b ("Reserved").

While this is technically incorrect, it is not reason enough to abort
BFPT parsing. Instead, continue BFPT parsing assuming there is no quad
enable bit present.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
---
 drivers/mtd/spi/spi-nor-core.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)
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Patch

diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index cdb464813b..b5b1ac8b5b 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -2100,7 +2100,8 @@  static int spi_nor_parse_bfpt(struct spi_nor *nor,
 		break;
 #endif
 	default:
-		return -EINVAL;
+		dev_dbg(nor->dev, "BFPT QER reserved value used\n");
+		break;
 	}
 
 	/* Stop here if JESD216 rev B. */