mbox series

[PULL] u-boot-riscv/master

Message ID 20210507010633.GB12714@andestech.com
State Accepted
Delegated to: Tom Rini
Headers show
Series [PULL] u-boot-riscv/master | expand

Pull-request

https://source.denx.de/u-boot/custodians/u-boot-riscv.git

Message

Leo Liang May 7, 2021, 1:06 a.m. UTC 
Hi Tom,

CI result: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7400

The following changes since commit 8ddaf943589756442bba21e5be645cd47526d82b:

  Merge tag 'dm-pull-29apr21' of https://source.denx.de/u-boot/custodians/u-boot-dm (2021-04-29 21:03:38 -0400)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git

for you to fetch changes up to 91e4b7516d84cefab7324765b3c8d6a909185ce2:

  cmd/exception: support ebreak exception on RISC-V (2021-05-05 16:13:12 +0800)

----------------------------------------------------------------
Dylan Jhong (1):
      atcspi200: Add timeout mechanism in spi_xfer()

Green Wan (2):
      riscv: cpu: Add callback to init each core
      riscv: cpu: fu740: clear feature disable CSR

Heinrich Schuchardt (1):
      cmd/exception: support ebreak exception on RISC-V

 arch/riscv/cpu/cpu.c        | 11 +++++++++++
 arch/riscv/cpu/fu540/spl.c  | 15 +++++++++++++++
 arch/riscv/cpu/start.S      |  4 ++++
 cmd/riscv/exception.c       | 10 ++++++++++
 doc/usage/exception.rst     |  3 +++
 drivers/spi/atcspi200_spi.c | 10 ++++++++--
 6 files changed, 51 insertions(+), 2 deletions(-)

Best regards,
Leo

Comments

Tom Rini May 7, 2021, 1:09 a.m. UTC | #1 
On Fri, May 07, 2021 at 09:06:33AM +0800, Leo Liang wrote:

> Hi Tom,
> 
> CI result: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7400
> 
> The following changes since commit 8ddaf943589756442bba21e5be645cd47526d82b:
> 
>   Merge tag 'dm-pull-29apr21' of https://source.denx.de/u-boot/custodians/u-boot-dm (2021-04-29 21:03:38 -0400)
> 
> are available in the Git repository at:
> 
>   https://source.denx.de/u-boot/custodians/u-boot-riscv.git
> 
> for you to fetch changes up to 91e4b7516d84cefab7324765b3c8d6a909185ce2:
> 
>   cmd/exception: support ebreak exception on RISC-V (2021-05-05 16:13:12 +0800)
> 
> ----------------------------------------------------------------
> Dylan Jhong (1):
>       atcspi200: Add timeout mechanism in spi_xfer()
> 
> Green Wan (2):
>       riscv: cpu: Add callback to init each core
>       riscv: cpu: fu740: clear feature disable CSR
> 
> Heinrich Schuchardt (1):
>       cmd/exception: support ebreak exception on RISC-V
> 
>  arch/riscv/cpu/cpu.c        | 11 +++++++++++
>  arch/riscv/cpu/fu540/spl.c  | 15 +++++++++++++++
>  arch/riscv/cpu/start.S      |  4 ++++
>  cmd/riscv/exception.c       | 10 ++++++++++
>  doc/usage/exception.rst     |  3 +++
>  drivers/spi/atcspi200_spi.c | 10 ++++++++--
>  6 files changed, 51 insertions(+), 2 deletions(-)

Please note that currently
https://patchwork.ozlabs.org/project/uboot/list/?series=&submitter=&state=&q=&archive=&delegate=20174
shows 55 patches.  Most of them have been posted long enough that I
would expect them to be applied if there's no further feedback.  Can you
please take a look?  Thanks!
Leo Liang May 7, 2021, 1:41 a.m. UTC | #2 
On Fri, May 07, 2021 at 09:09:43AM +0800, Tom Rini wrote:
> On Fri, May 07, 2021 at 09:06:33AM +0800, Leo Liang wrote:
> 
> > Hi Tom,
> > 
> > CI result: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7400
> > 
> > The following changes since commit 8ddaf943589756442bba21e5be645cd47526d82b:
> > 
> >   Merge tag 'dm-pull-29apr21' of https://source.denx.de/u-boot/custodians/u-boot-dm (2021-04-29 21:03:38 -0400)
> > 
> > are available in the Git repository at:
> > 
> >   https://source.denx.de/u-boot/custodians/u-boot-riscv.git
> > 
> > for you to fetch changes up to 91e4b7516d84cefab7324765b3c8d6a909185ce2:
> > 
> >   cmd/exception: support ebreak exception on RISC-V (2021-05-05 16:13:12 +0800)
> > 
> > ----------------------------------------------------------------
> > Dylan Jhong (1):
> >       atcspi200: Add timeout mechanism in spi_xfer()
> > 
> > Green Wan (2):
> >       riscv: cpu: Add callback to init each core
> >       riscv: cpu: fu740: clear feature disable CSR
> > 
> > Heinrich Schuchardt (1):
> >       cmd/exception: support ebreak exception on RISC-V
> > 
> >  arch/riscv/cpu/cpu.c        | 11 +++++++++++
> >  arch/riscv/cpu/fu540/spl.c  | 15 +++++++++++++++
> >  arch/riscv/cpu/start.S      |  4 ++++
> >  cmd/riscv/exception.c       | 10 ++++++++++
> >  doc/usage/exception.rst     |  3 +++
> >  drivers/spi/atcspi200_spi.c | 10 ++++++++--
> >  6 files changed, 51 insertions(+), 2 deletions(-)
> 
> Please note that currently
> https://patchwork.ozlabs.org/project/uboot/list/?series=&submitter=&state=&q=&archive=&delegate=20174
> shows 55 patches.  Most of them have been posted long enough that I
> would expect them to be applied if there's no further feedback.  Can you
> please take a look?  Thanks!
> 

No problem, sorry for the delay!

Two quick questions.

Some of the patches delegated to Andes do not own a RISC-V tag but rather clk or driver etc.
Do you mind if we pull them through RISC-V tree?

And for these patches, 
do you prefer them pulled into this release or for-next branch?

Best regards,
Leo
Sean Anderson May 7, 2021, 1:49 a.m. UTC | #3 
Hi Leo,

Are you maintaining RISC-V now? Should I be CC-ing you on my series?
Can you update MAINTAINERS with this information? Thanks.

--Sean

On 5/6/21 9:06 PM, Leo Liang wrote:
> Hi Tom,
> 
> CI result: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7400
> 
> The following changes since commit 8ddaf943589756442bba21e5be645cd47526d82b:
> 
>    Merge tag 'dm-pull-29apr21' of https://source.denx.de/u-boot/custodians/u-boot-dm (2021-04-29 21:03:38 -0400)
> 
> are available in the Git repository at:
> 
>    https://source.denx.de/u-boot/custodians/u-boot-riscv.git
> 
> for you to fetch changes up to 91e4b7516d84cefab7324765b3c8d6a909185ce2:
> 
>    cmd/exception: support ebreak exception on RISC-V (2021-05-05 16:13:12 +0800)
> 
> ----------------------------------------------------------------
> Dylan Jhong (1):
>        atcspi200: Add timeout mechanism in spi_xfer()
> 
> Green Wan (2):
>        riscv: cpu: Add callback to init each core
>        riscv: cpu: fu740: clear feature disable CSR
> 
> Heinrich Schuchardt (1):
>        cmd/exception: support ebreak exception on RISC-V
> 
>   arch/riscv/cpu/cpu.c        | 11 +++++++++++
>   arch/riscv/cpu/fu540/spl.c  | 15 +++++++++++++++
>   arch/riscv/cpu/start.S      |  4 ++++
>   cmd/riscv/exception.c       | 10 ++++++++++
>   doc/usage/exception.rst     |  3 +++
>   drivers/spi/atcspi200_spi.c | 10 ++++++++--
>   6 files changed, 51 insertions(+), 2 deletions(-)
> 
> Best regards,
> Leo
>
Sean Anderson May 7, 2021, 1:55 a.m. UTC | #4 
On 5/6/21 9:41 PM, Leo Liang wrote:
> On Fri, May 07, 2021 at 09:09:43AM +0800, Tom Rini wrote:
>> On Fri, May 07, 2021 at 09:06:33AM +0800, Leo Liang wrote:
>>
>>> Hi Tom,
>>>
>>> CI result: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7400
>>>
>>> The following changes since commit 8ddaf943589756442bba21e5be645cd47526d82b:
>>>
>>>    Merge tag 'dm-pull-29apr21' of https://source.denx.de/u-boot/custodians/u-boot-dm (2021-04-29 21:03:38 -0400)
>>>
>>> are available in the Git repository at:
>>>
>>>    https://source.denx.de/u-boot/custodians/u-boot-riscv.git
>>>
>>> for you to fetch changes up to 91e4b7516d84cefab7324765b3c8d6a909185ce2:
>>>
>>>    cmd/exception: support ebreak exception on RISC-V (2021-05-05 16:13:12 +0800)
>>>
>>> ----------------------------------------------------------------
>>> Dylan Jhong (1):
>>>        atcspi200: Add timeout mechanism in spi_xfer()
>>>
>>> Green Wan (2):
>>>        riscv: cpu: Add callback to init each core
>>>        riscv: cpu: fu740: clear feature disable CSR
>>>
>>> Heinrich Schuchardt (1):
>>>        cmd/exception: support ebreak exception on RISC-V
>>>
>>>   arch/riscv/cpu/cpu.c        | 11 +++++++++++
>>>   arch/riscv/cpu/fu540/spl.c  | 15 +++++++++++++++
>>>   arch/riscv/cpu/start.S      |  4 ++++
>>>   cmd/riscv/exception.c       | 10 ++++++++++
>>>   doc/usage/exception.rst     |  3 +++
>>>   drivers/spi/atcspi200_spi.c | 10 ++++++++--
>>>   6 files changed, 51 insertions(+), 2 deletions(-)
>>
>> Please note that currently
>> https://patchwork.ozlabs.org/project/uboot/list/?series=&submitter=&state=&q=&archive=&delegate=20174
>> shows 55 patches.  Most of them have been posted long enough that I
>> would expect them to be applied if there's no further feedback.  Can you
>> please take a look?  Thanks!
>>
> 
> No problem, sorry for the delay!
> 
> Two quick questions.
> 
> Some of the patches delegated to Andes do not own a RISC-V tag but rather clk or driver etc.
> Do you mind if we pull them through RISC-V tree?

Clock patches should go though Lukasz's tree, but given the scope of the
patches I think it is OK for them to be in RISC-V. I would like to get an
Acked-by from him, but unfortunately he hasn't commented on them at all.

--Sean

> And for these patches,
> do you prefer them pulled into this release or for-next branch?
> 
> Best regards,
> Leo
>
Dimitri John Ledkov May 7, 2021, 2:21 p.m. UTC | #5 
Hi,

On Fri, May 7, 2021 at 2:42 AM Leo Liang <ycliang@andestech.com> wrote:
>
> On Fri, May 07, 2021 at 09:09:43AM +0800, Tom Rini wrote:
> > On Fri, May 07, 2021 at 09:06:33AM +0800, Leo Liang wrote:
> >
> > > Hi Tom,
> > >
> > > CI result: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7400
> > >
> > > The following changes since commit 8ddaf943589756442bba21e5be645cd47526d82b:
> > >
> > >   Merge tag 'dm-pull-29apr21' of https://source.denx.de/u-boot/custodians/u-boot-dm (2021-04-29 21:03:38 -0400)
> > >
> > > are available in the Git repository at:
> > >
> > >   https://source.denx.de/u-boot/custodians/u-boot-riscv.git
> > >
> > > for you to fetch changes up to 91e4b7516d84cefab7324765b3c8d6a909185ce2:
> > >
> > >   cmd/exception: support ebreak exception on RISC-V (2021-05-05 16:13:12 +0800)
> > >
> > > ----------------------------------------------------------------
> > > Dylan Jhong (1):
> > >       atcspi200: Add timeout mechanism in spi_xfer()
> > >
> > > Green Wan (2):
> > >       riscv: cpu: Add callback to init each core
> > >       riscv: cpu: fu740: clear feature disable CSR
> > >
> > > Heinrich Schuchardt (1):
> > >       cmd/exception: support ebreak exception on RISC-V
> > >
> > >  arch/riscv/cpu/cpu.c        | 11 +++++++++++
> > >  arch/riscv/cpu/fu540/spl.c  | 15 +++++++++++++++
> > >  arch/riscv/cpu/start.S      |  4 ++++
> > >  cmd/riscv/exception.c       | 10 ++++++++++
> > >  doc/usage/exception.rst     |  3 +++
> > >  drivers/spi/atcspi200_spi.c | 10 ++++++++--
> > >  6 files changed, 51 insertions(+), 2 deletions(-)
> >
> > Please note that currently
> > https://patchwork.ozlabs.org/project/uboot/list/?series=&submitter=&state=&q=&archive=&delegate=20174
> > shows 55 patches.  Most of them have been posted long enough that I
> > would expect them to be applied if there's no further feedback.  Can you
> > please take a look?  Thanks!
> >
>
> No problem, sorry for the delay!
>
> Two quick questions.
>
> Some of the patches delegated to Andes do not own a RISC-V tag but rather clk or driver etc.
> Do you mind if we pull them through RISC-V tree?
>
> And for these patches,
> do you prefer them pulled into this release or for-next branch?


Although https://patchwork.ozlabs.org/project/uboot/patch/20210421114201.57994-1-xnox@ubuntu.com/
is not strictly for riscv64 it does prevent me from using the same
Ubuntu rootfs for riscv boards or qemu. I would appreciate it if it
could be pulled in via qemu or riscv maintainers.
Tom Rini May 7, 2021, 2:35 p.m. UTC | #6 
On Fri, May 07, 2021 at 03:21:13PM +0100, Dimitri John Ledkov wrote:
> Hi,
> 
> On Fri, May 7, 2021 at 2:42 AM Leo Liang <ycliang@andestech.com> wrote:
> >
> > On Fri, May 07, 2021 at 09:09:43AM +0800, Tom Rini wrote:
> > > On Fri, May 07, 2021 at 09:06:33AM +0800, Leo Liang wrote:
> > >
> > > > Hi Tom,
> > > >
> > > > CI result: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7400
> > > >
> > > > The following changes since commit 8ddaf943589756442bba21e5be645cd47526d82b:
> > > >
> > > >   Merge tag 'dm-pull-29apr21' of https://source.denx.de/u-boot/custodians/u-boot-dm (2021-04-29 21:03:38 -0400)
> > > >
> > > > are available in the Git repository at:
> > > >
> > > >   https://source.denx.de/u-boot/custodians/u-boot-riscv.git
> > > >
> > > > for you to fetch changes up to 91e4b7516d84cefab7324765b3c8d6a909185ce2:
> > > >
> > > >   cmd/exception: support ebreak exception on RISC-V (2021-05-05 16:13:12 +0800)
> > > >
> > > > ----------------------------------------------------------------
> > > > Dylan Jhong (1):
> > > >       atcspi200: Add timeout mechanism in spi_xfer()
> > > >
> > > > Green Wan (2):
> > > >       riscv: cpu: Add callback to init each core
> > > >       riscv: cpu: fu740: clear feature disable CSR
> > > >
> > > > Heinrich Schuchardt (1):
> > > >       cmd/exception: support ebreak exception on RISC-V
> > > >
> > > >  arch/riscv/cpu/cpu.c        | 11 +++++++++++
> > > >  arch/riscv/cpu/fu540/spl.c  | 15 +++++++++++++++
> > > >  arch/riscv/cpu/start.S      |  4 ++++
> > > >  cmd/riscv/exception.c       | 10 ++++++++++
> > > >  doc/usage/exception.rst     |  3 +++
> > > >  drivers/spi/atcspi200_spi.c | 10 ++++++++--
> > > >  6 files changed, 51 insertions(+), 2 deletions(-)
> > >
> > > Please note that currently
> > > https://patchwork.ozlabs.org/project/uboot/list/?series=&submitter=&state=&q=&archive=&delegate=20174
> > > shows 55 patches.  Most of them have been posted long enough that I
> > > would expect them to be applied if there's no further feedback.  Can you
> > > please take a look?  Thanks!
> > >
> >
> > No problem, sorry for the delay!
> >
> > Two quick questions.
> >
> > Some of the patches delegated to Andes do not own a RISC-V tag but rather clk or driver etc.
> > Do you mind if we pull them through RISC-V tree?
> >
> > And for these patches,
> > do you prefer them pulled into this release or for-next branch?
> 
> 
> Although https://patchwork.ozlabs.org/project/uboot/patch/20210421114201.57994-1-xnox@ubuntu.com/
> is not strictly for riscv64 it does prevent me from using the same
> Ubuntu rootfs for riscv boards or qemu. I would appreciate it if it
> could be pulled in via qemu or riscv maintainers.

As that's a PXE change I've assigned it to the network maintainer, and
I've cc'd him here.  Thanks.
Tom Rini May 7, 2021, 3:37 p.m. UTC | #7 
On Fri, May 07, 2021 at 09:06:33AM +0800, Leo Liang wrote:

> Hi Tom,
> 
> CI result: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7400
> 
> The following changes since commit 8ddaf943589756442bba21e5be645cd47526d82b:
> 
>   Merge tag 'dm-pull-29apr21' of https://source.denx.de/u-boot/custodians/u-boot-dm (2021-04-29 21:03:38 -0400)
> 
> are available in the Git repository at:
> 
>   https://source.denx.de/u-boot/custodians/u-boot-riscv.git
> 
> for you to fetch changes up to 91e4b7516d84cefab7324765b3c8d6a909185ce2:
> 
>   cmd/exception: support ebreak exception on RISC-V (2021-05-05 16:13:12 +0800)
> 

Applied to u-boot/master, thanks!
Tom Rini May 7, 2021, 4:15 p.m. UTC | #8 
On Thu, May 06, 2021 at 09:55:17PM -0400, Sean Anderson wrote:
> On 5/6/21 9:41 PM, Leo Liang wrote:
> > On Fri, May 07, 2021 at 09:09:43AM +0800, Tom Rini wrote:
> > > On Fri, May 07, 2021 at 09:06:33AM +0800, Leo Liang wrote:
> > > 
> > > > Hi Tom,
> > > > 
> > > > CI result: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7400
> > > > 
> > > > The following changes since commit 8ddaf943589756442bba21e5be645cd47526d82b:
> > > > 
> > > >    Merge tag 'dm-pull-29apr21' of https://source.denx.de/u-boot/custodians/u-boot-dm (2021-04-29 21:03:38 -0400)
> > > > 
> > > > are available in the Git repository at:
> > > > 
> > > >    https://source.denx.de/u-boot/custodians/u-boot-riscv.git
> > > > 
> > > > for you to fetch changes up to 91e4b7516d84cefab7324765b3c8d6a909185ce2:
> > > > 
> > > >    cmd/exception: support ebreak exception on RISC-V (2021-05-05 16:13:12 +0800)
> > > > 
> > > > ----------------------------------------------------------------
> > > > Dylan Jhong (1):
> > > >        atcspi200: Add timeout mechanism in spi_xfer()
> > > > 
> > > > Green Wan (2):
> > > >        riscv: cpu: Add callback to init each core
> > > >        riscv: cpu: fu740: clear feature disable CSR
> > > > 
> > > > Heinrich Schuchardt (1):
> > > >        cmd/exception: support ebreak exception on RISC-V
> > > > 
> > > >   arch/riscv/cpu/cpu.c        | 11 +++++++++++
> > > >   arch/riscv/cpu/fu540/spl.c  | 15 +++++++++++++++
> > > >   arch/riscv/cpu/start.S      |  4 ++++
> > > >   cmd/riscv/exception.c       | 10 ++++++++++
> > > >   doc/usage/exception.rst     |  3 +++
> > > >   drivers/spi/atcspi200_spi.c | 10 ++++++++--
> > > >   6 files changed, 51 insertions(+), 2 deletions(-)
> > > 
> > > Please note that currently
> > > https://patchwork.ozlabs.org/project/uboot/list/?series=&submitter=&state=&q=&archive=&delegate=20174
> > > shows 55 patches.  Most of them have been posted long enough that I
> > > would expect them to be applied if there's no further feedback.  Can you
> > > please take a look?  Thanks!
> > > 
> > 
> > No problem, sorry for the delay!
> > 
> > Two quick questions.
> > 
> > Some of the patches delegated to Andes do not own a RISC-V tag but rather clk or driver etc.
> > Do you mind if we pull them through RISC-V tree?
> 
> Clock patches should go though Lukasz's tree, but given the scope of the
> patches I think it is OK for them to be in RISC-V. I would like to get an
> Acked-by from him, but unfortunately he hasn't commented on them at all.

In general, I believe it is OK for non-subsystem-core changes to go via
the architecture / SoC tree.
Leo Liang May 10, 2021, 6:57 a.m. UTC | #9 
On Fri, May 07, 2021 at 09:49:08AM +0800, Sean Anderson wrote:
> Hi Leo,
> 
> Are you maintaining RISC-V now? Should I be CC-ing you on my series?
> Can you update MAINTAINERS with this information? Thanks.
> 
> --Sean
> 

Hi Sean,

Yes, I am now co-maintaining RISC-V tree with Rick.
I will update the information as soon as possible, thanks for the reminder.
And yes, please do CC your work to me, thanks again!

Best regards,
Leo

> On 5/6/21 9:06 PM, Leo Liang wrote:
> > Hi Tom,
> > 
> > CI result: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7400
> > 
> > The following changes since commit 8ddaf943589756442bba21e5be645cd47526d82b:
> > 
> >    Merge tag 'dm-pull-29apr21' of https://source.denx.de/u-boot/custodians/u-boot-dm (2021-04-29 21:03:38 -0400)
> > 
> > are available in the Git repository at:
> > 
> >    https://source.denx.de/u-boot/custodians/u-boot-riscv.git
> > 
> > for you to fetch changes up to 91e4b7516d84cefab7324765b3c8d6a909185ce2:
> > 
> >    cmd/exception: support ebreak exception on RISC-V (2021-05-05 16:13:12 +0800)
> > 
> > ----------------------------------------------------------------
> > Dylan Jhong (1):
> >        atcspi200: Add timeout mechanism in spi_xfer()
> > 
> > Green Wan (2):
> >        riscv: cpu: Add callback to init each core
> >        riscv: cpu: fu740: clear feature disable CSR
> > 
> > Heinrich Schuchardt (1):
> >        cmd/exception: support ebreak exception on RISC-V
> > 
> >   arch/riscv/cpu/cpu.c        | 11 +++++++++++
> >   arch/riscv/cpu/fu540/spl.c  | 15 +++++++++++++++
> >   arch/riscv/cpu/start.S      |  4 ++++
> >   cmd/riscv/exception.c       | 10 ++++++++++
> >   doc/usage/exception.rst     |  3 +++
> >   drivers/spi/atcspi200_spi.c | 10 ++++++++--
> >   6 files changed, 51 insertions(+), 2 deletions(-)
> > 
> > Best regards,
> > Leo
> >