| Message ID | 20210505125305.20564-1-andre.przywara@arm.com |
|---|---|
| State | Accepted |
| Delegated to: | Andre Przywara |
| Headers | show |
| Series | [v2] sunxi: clock: H6/H616: Fix PLL clock factor encodings | expand |
On Wed, 5 May 2021 13:53:05 +0100 Andre Przywara <andre.przywara@arm.com> wrote: Hi, > Most clock factors and dividers in the H6 PLLs use a "+1 encoding", > which we were missing on two occasions. can someone please confirm that I didn't mess this up? Cheers, Andre > > This fixes the MMC clock setup on the H6, which could be slightly off due > to the wrong parent frequency: > mmc 2 set mod-clk req 52000000 parent 1176000000 n 2 m 12 rate 49000000 > > Also the CPU frequency was a tad too high before. > > Signed-off-by: Andre Przywara <andre.przywara@arm.com> > --- > Changelog v1 .. v2: > - Also fix PLL5 factor calculation (video, currently unused) > - Also fix PLL1 factor calculation (CPU clock) > > arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h | 4 ++-- > arch/arm/mach-sunxi/clock_sun50i_h6.c | 2 +- > 2 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h > index 62abfc4ef6b..2e076cf594d 100644 > --- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h > +++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h > @@ -233,14 +233,14 @@ struct sunxi_ccm_reg { > #define CCM_PLL1_OUT_EN BIT(27) > #define CCM_PLL1_CLOCK_TIME_2 (2 << 24) > #define CCM_PLL1_CTRL_P(p) ((p) << 16) > -#define CCM_PLL1_CTRL_N(n) ((n) << 8) > +#define CCM_PLL1_CTRL_N(n) (((n) - 1) << 8) > > /* pll5 bit field */ > #define CCM_PLL5_CTRL_EN BIT(31) > #define CCM_PLL5_LOCK_EN BIT(29) > #define CCM_PLL5_LOCK BIT(28) > #define CCM_PLL5_OUT_EN BIT(27) > -#define CCM_PLL5_CTRL_N(n) ((n) << 8) > +#define CCM_PLL5_CTRL_N(n) (((n) - 1) << 8) > #define CCM_PLL5_CTRL_DIV1(div1) ((div1) << 0) > #define CCM_PLL5_CTRL_DIV2(div0) ((div0) << 1) > > diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c > index 492fc4a3fca..a947463e0a5 100644 > --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c > +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c > @@ -94,7 +94,7 @@ unsigned int clock_get_pll6(void) > int m = IS_ENABLED(CONFIG_MACH_SUN50I_H6) ? 4 : 2; > > uint32_t rval = readl(&ccm->pll6_cfg); > - int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT); > + int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1; > int div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >> > CCM_PLL6_CTRL_DIV1_SHIFT) + 1; > int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >>
Hi! Dne četrtek, 27. maj 2021 ob 01:49:48 CEST je Andre Przywara napisal(a): > On Wed, 5 May 2021 13:53:05 +0100 > Andre Przywara <andre.przywara@arm.com> wrote: > > Hi, > > > Most clock factors and dividers in the H6 PLLs use a "+1 encoding", > > which we were missing on two occasions. > > can someone please confirm that I didn't mess this up? > > Cheers, > Andre > > > This fixes the MMC clock setup on the H6, which could be slightly off due > > to the wrong parent frequency: > > mmc 2 set mod-clk req 52000000 parent 1176000000 n 2 m 12 rate 49000000 > > > > Also the CPU frequency was a tad too high before. > > > > Signed-off-by: Andre Przywara <andre.przywara@arm.com> > > --- > > Changelog v1 .. v2: > > - Also fix PLL5 factor calculation (video, currently unused) > > - Also fix PLL1 factor calculation (CPU clock) > > > > arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h | 4 ++-- > > arch/arm/mach-sunxi/clock_sun50i_h6.c | 2 +- > > 2 files changed, 3 insertions(+), 3 deletions(-) > > > > diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h > > b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h index > > 62abfc4ef6b..2e076cf594d 100644 > > --- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h > > +++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h > > @@ -233,14 +233,14 @@ struct sunxi_ccm_reg { > > > > #define CCM_PLL1_OUT_EN BIT(27) > > #define CCM_PLL1_CLOCK_TIME_2 (2 << 24) > > #define CCM_PLL1_CTRL_P(p) ((p) << 16) > > > > -#define CCM_PLL1_CTRL_N(n) ((n) << 8) > > +#define CCM_PLL1_CTRL_N(n) (((n) - 1) << 8) > > > > /* pll5 bit field */ > > #define CCM_PLL5_CTRL_EN BIT(31) > > #define CCM_PLL5_LOCK_EN BIT(29) > > #define CCM_PLL5_LOCK BIT(28) > > #define CCM_PLL5_OUT_EN BIT(27) > > > > -#define CCM_PLL5_CTRL_N(n) ((n) << 8) > > +#define CCM_PLL5_CTRL_N(n) (((n) - 1) << 8) H6 and H616 DRAM drivers actually consider this "- 1" in the code. Either drop this change or fix DRAM drivers. With that: Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Best regards, Jernej > > > > #define CCM_PLL5_CTRL_DIV1(div1) ((div1) << 0) > > #define CCM_PLL5_CTRL_DIV2(div0) ((div0) << 1) > > > > diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c > > b/arch/arm/mach-sunxi/clock_sun50i_h6.c index 492fc4a3fca..a947463e0a5 > > 100644 > > --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c > > +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c > > @@ -94,7 +94,7 @@ unsigned int clock_get_pll6(void) > > > > int m = IS_ENABLED(CONFIG_MACH_SUN50I_H6) ? 4 : 2; > > > > uint32_t rval = readl(&ccm->pll6_cfg); > > > > - int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT); > > + int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1; > > > > int div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >> > > > > CCM_PLL6_CTRL_DIV1_SHIFT) + 1; > > > > int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >>
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h index 62abfc4ef6b..2e076cf594d 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h @@ -233,14 +233,14 @@ struct sunxi_ccm_reg { #define CCM_PLL1_OUT_EN BIT(27) #define CCM_PLL1_CLOCK_TIME_2 (2 << 24) #define CCM_PLL1_CTRL_P(p) ((p) << 16) -#define CCM_PLL1_CTRL_N(n) ((n) << 8) +#define CCM_PLL1_CTRL_N(n) (((n) - 1) << 8) /* pll5 bit field */ #define CCM_PLL5_CTRL_EN BIT(31) #define CCM_PLL5_LOCK_EN BIT(29) #define CCM_PLL5_LOCK BIT(28) #define CCM_PLL5_OUT_EN BIT(27) -#define CCM_PLL5_CTRL_N(n) ((n) << 8) +#define CCM_PLL5_CTRL_N(n) (((n) - 1) << 8) #define CCM_PLL5_CTRL_DIV1(div1) ((div1) << 0) #define CCM_PLL5_CTRL_DIV2(div0) ((div0) << 1) diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c index 492fc4a3fca..a947463e0a5 100644 --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c @@ -94,7 +94,7 @@ unsigned int clock_get_pll6(void) int m = IS_ENABLED(CONFIG_MACH_SUN50I_H6) ? 4 : 2; uint32_t rval = readl(&ccm->pll6_cfg); - int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT); + int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1; int div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >> CCM_PLL6_CTRL_DIV1_SHIFT) + 1; int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >>
Most clock factors and dividers in the H6 PLLs use a "+1 encoding", which we were missing on two occasions. This fixes the MMC clock setup on the H6, which could be slightly off due to the wrong parent frequency: mmc 2 set mod-clk req 52000000 parent 1176000000 n 2 m 12 rate 49000000 Also the CPU frequency was a tad too high before. Signed-off-by: Andre Przywara <andre.przywara@arm.com> --- Changelog v1 .. v2: - Also fix PLL5 factor calculation (video, currently unused) - Also fix PLL1 factor calculation (CPU clock) arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h | 4 ++-- arch/arm/mach-sunxi/clock_sun50i_h6.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-)