From patchwork Wed May 5 09:41:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 1474225 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=PHc6hqdy; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FZsGJ56Q8z9sVb for ; Wed, 5 May 2021 19:43:20 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id BAD4282CF3; Wed, 5 May 2021 11:42:20 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="PHc6hqdy"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 1B64982CE6; Wed, 5 May 2021 11:42:13 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id BD60F82CC2 for ; Wed, 5 May 2021 11:42:09 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=p.yadav@ti.com Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 1459g35S129208; Wed, 5 May 2021 04:42:03 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1620207723; bh=RReUGtGpNnNXCc0ZMLSDsReheXlQwCHWX+DRZvoinoc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=PHc6hqdyjZA2pPnyqkrasiBiU2sDfS6eEKHd+f+pOAl734G4dQ3vMlKPSYzetR5m+ 99Vp7CA9H++OtjECCnzctJr8frgo34OI2bfpE3pvDwGJe0VcJNeYUd17wfYlT/6dCx HVjFpNeJS6X63NWVK/aVpgXd+/lyiMuhN4Fh6cwY= Received: from DLEE103.ent.ti.com (dlee103.ent.ti.com [157.170.170.33]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 1459g1jY030134 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 5 May 2021 04:42:03 -0500 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Wed, 5 May 2021 04:42:03 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Wed, 5 May 2021 04:42:02 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 1459fcKp053048; Wed, 5 May 2021 04:42:00 -0500 From: Pratyush Yadav To: Chris Packham , Jagan Teki , Vignesh R , Ryder Lee , Weijie Gao , Chunfeng Yun , GSS_MTK_Uboot_upstream , CC: Pratyush Yadav , Takahiro Kuwano , Sean Anderson Subject: [PATCH v9 06/28] spi: cadence-qspi: Add a small delay before indirect writes Date: Wed, 5 May 2021 15:11:16 +0530 Message-ID: <20210505094138.30805-7-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210505094138.30805-1-p.yadav@ti.com> References: <20210505094138.30805-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean Once the start bit is toggled it takes a small amount of time before it is internally synchronized. This means we can't start writing during that part. So add a small delay to allow the bit to be synchronized. Signed-off-by: Pratyush Yadav --- drivers/spi/cadence_qspi.c | 4 ++++ drivers/spi/cadence_qspi.h | 1 + drivers/spi/cadence_qspi_apb.c | 6 ++++++ 3 files changed, 11 insertions(+) diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index de7628de27..a961193cdc 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -20,6 +20,8 @@ #include #include "cadence_qspi.h" +#define NSEC_PER_SEC 1000000000L + #define CQSPI_STIG_READ 0 #define CQSPI_STIG_WRITE 1 #define CQSPI_READ 2 @@ -208,6 +210,8 @@ static int cadence_spi_probe(struct udevice *bus) priv->qspi_is_init = 1; } + plat->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, plat->ref_clk_hz); + return 0; } diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index b06d7750e2..5c745541a6 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -27,6 +27,7 @@ struct cadence_spi_plat { fdt_addr_t ahbsize; bool use_dac_mode; int read_delay; + u32 wr_delay; /* Flash parameters */ u32 page_size; diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index b051f462ed..92e57730bd 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -730,6 +730,12 @@ cadence_qspi_apb_indirect_write_execute(struct cadence_spi_plat *plat, writel(CQSPI_REG_INDIRECTWR_START, plat->regbase + CQSPI_REG_INDIRECTWR); + /* + * Some delay is required for the above bit to be internally + * synchronized by the QSPI module. + */ + ndelay(plat->wr_delay); + while (remaining > 0) { write_bytes = remaining > page_size ? page_size : remaining; writesl(plat->ahbbase, bb_txbuf, write_bytes >> 2);