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From: Pratyush Yadav
To: Chris Packham , Jagan Teki
, Vignesh R , Ryder Lee
, Weijie Gao ,
Chunfeng Yun , GSS_MTK_Uboot_upstream
,
CC: Pratyush Yadav , Takahiro Kuwano
, Sean Anderson
Subject: [PATCH v9 09/28] mtd: spi-nor-core: Fix address width on flash chips
> 16MB
Date: Wed, 5 May 2021 15:11:19 +0530
Message-ID: <20210505094138.30805-10-p.yadav@ti.com>
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If a flash chip has more than 16MB capacity but its BFPT reports
BFPT_DWORD1_ADDRESS_BYTES_3_OR_4, the spi-nor framework defaults to 3.
The check in spi_nor_scan() doesn't catch it because addr_width did get
set. This fixes that check.
Ported from Kernel commit 324f78dfb442b82365548b657ec4e6974c677502.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index a6625535a7..db918fc06f 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -2602,7 +2602,11 @@ int spi_nor_scan(struct spi_nor *nor)
/* already configured from SFDP */
} else if (info->addr_width) {
nor->addr_width = info->addr_width;
- } else if (mtd->size > SZ_16M) {
+ } else {
+ nor->addr_width = 3;
+ }
+
+ if (nor->addr_width == 3 && mtd->size > SZ_16M) {
#ifndef CONFIG_SPI_FLASH_BAR
/* enable 4-byte addressing if the device exceeds 16MiB */
nor->addr_width = 4;
@@ -2616,8 +2620,6 @@ int spi_nor_scan(struct spi_nor *nor)
if (ret < 0)
return ret;
#endif
- } else {
- nor->addr_width = 3;
}
if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {