diff mbox series

[1/2] riscv: cpu: Add callback to init each core

Message ID 20210503062306.349882-1-green.wan@sifive.com
State Accepted
Commit edd9ad81947d2136c71657be88d6cc35a56bd22f
Delegated to: Andes
Headers show
Series [1/2] riscv: cpu: Add callback to init each core | expand

Commit Message

Green Wan May 3, 2021, 6:23 a.m. UTC 
Add a callback harts_early_init() to start.S to allow different riscv
hart perform setup code for each hart as early as possible. Since all
the harts enter the callback, they must be able to run the same
setup.

Signed-off-by: Green Wan <green.wan@sifive.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
 arch/riscv/cpu/cpu.c   | 11 +++++++++++
 arch/riscv/cpu/start.S |  4 ++++
 2 files changed, 15 insertions(+)
diff mbox series

Patch

diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index 85592f5bee..296e458db4 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -140,3 +140,14 @@  int arch_early_init_r(void)
 {
 	return riscv_cpu_probe();
 }
+
+/**
+ * harts_early_init() - A callback function called by start.S to configure
+ * feature settings of each hart.
+ *
+ * In a multi-core system, memory access shall be careful here, it shall
+ * take care of race conditions.
+ */
+__weak void harts_early_init(void)
+{
+}
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 8589509e01..308b0a97a5 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -117,6 +117,10 @@  call_board_init_f_0:
 	mv	sp, a0
 #endif
 
+	/* Configure proprietary settings and customized CSRs of harts */
+call_harts_early_init:
+	jal	harts_early_init
+
 #ifndef CONFIG_XIP
 	/*
 	 * Pick hart to initialize global data and run U-Boot. The other harts