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Thu, 08 Apr 2021 00:50:52 -0700 (PDT) From: Neil Armstrong To: u-boot@lists.denx.de Cc: u-boot-amlogic@groups.io, Neil Armstrong Subject: [PATCH 2/5] phy: meson-g12a-usb3-pcie: add support for PCIe ops Date: Thu, 8 Apr 2021 09:50:44 +0200 Message-Id: <20210408075047.4076954-3-narmstrong@baylibre.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210408075047.4076954-1-narmstrong@baylibre.com> References: <20210408075047.4076954-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean Add the PCIe part of the G12A USB3 PCIe Combo PHY driver. Signed-off-by: Neil Armstrong --- drivers/phy/meson-g12a-usb3-pcie.c | 81 ++++++++++++++++++++++++++++-- 1 file changed, 77 insertions(+), 4 deletions(-) diff --git a/drivers/phy/meson-g12a-usb3-pcie.c b/drivers/phy/meson-g12a-usb3-pcie.c index 0433d93474..8f72b5a6a7 100644 --- a/drivers/phy/meson-g12a-usb3-pcie.c +++ b/drivers/phy/meson-g12a-usb3-pcie.c @@ -23,6 +23,9 @@ #include #include +#define PHY_TYPE_PCIE 2 +#define PHY_TYPE_USB3 4 + #define PHY_R0 0x00 #define PHY_R0_PCIE_POWER_STATE GENMASK(4, 0) #define PHY_R0_PCIE_USB3_SWITCH GENMASK(6, 5) @@ -55,6 +58,8 @@ #define PHY_R5_PHY_CR_ACK BIT(16) #define PHY_R5_PHY_BS_OUT BIT(17) +#define PCIE_RESET_DELAY 500 + struct phy_g12a_usb3_pcie_priv { struct regmap *regmap; #if CONFIG_IS_ENABLED(CLK) @@ -202,8 +207,6 @@ static int phy_meson_g12a_usb3_init(struct phy *phy) unsigned int data; int ret; - /* TOFIX Handle PCIE mode */ - ret = reset_assert_bulk(&priv->resets); udelay(1); ret |= reset_deassert_bulk(&priv->resets); @@ -296,9 +299,79 @@ static int phy_meson_g12a_usb3_exit(struct phy *phy) return reset_assert_bulk(&priv->resets); } +static int phy_meson_g12a_usb3_pcie_init(struct phy *phy) +{ + if (phy->id == PHY_TYPE_USB3) + return phy_meson_g12a_usb3_init(phy); + + return 0; +} + +static int phy_meson_g12a_usb3_pcie_exit(struct phy *phy) +{ + if (phy->id == PHY_TYPE_USB3) + return phy_meson_g12a_usb3_exit(phy); + + return 0; +} + +static int phy_meson_g12a_usb3_pcie_power_on(struct phy *phy) +{ + struct phy_g12a_usb3_pcie_priv *priv = dev_get_priv(phy->dev); + + if (phy->id == PHY_TYPE_USB3) + return 0; + + regmap_update_bits(priv->regmap, PHY_R0, + PHY_R0_PCIE_POWER_STATE, + FIELD_PREP(PHY_R0_PCIE_POWER_STATE, 0x1c)); + + return 0; +} + +static int phy_meson_g12a_usb3_pcie_power_off(struct phy *phy) +{ + struct phy_g12a_usb3_pcie_priv *priv = dev_get_priv(phy->dev); + + if (phy->id == PHY_TYPE_USB3) + return 0; + + regmap_update_bits(priv->regmap, PHY_R0, + PHY_R0_PCIE_POWER_STATE, + FIELD_PREP(PHY_R0_PCIE_POWER_STATE, 0x1d)); + + return 0; +} + +static int phy_meson_g12a_usb3_pcie_reset(struct phy *phy) +{ + struct phy_g12a_usb3_pcie_priv *priv = dev_get_priv(phy->dev); + int ret; + + if (phy->id == PHY_TYPE_USB3) + return 0; + + ret = reset_assert_bulk(&priv->resets); + if (ret) + return ret; + + udelay(PCIE_RESET_DELAY); + + ret = reset_deassert_bulk(&priv->resets); + if (ret) + return ret; + + udelay(PCIE_RESET_DELAY); + + return 0; +} + struct phy_ops meson_g12a_usb3_pcie_phy_ops = { - .init = phy_meson_g12a_usb3_init, - .exit = phy_meson_g12a_usb3_exit, + .init = phy_meson_g12a_usb3_pcie_init, + .exit = phy_meson_g12a_usb3_pcie_exit, + .power_on = phy_meson_g12a_usb3_pcie_power_on, + .power_off = phy_meson_g12a_usb3_pcie_power_off, + .reset = phy_meson_g12a_usb3_pcie_reset, }; int meson_g12a_usb3_pcie_phy_probe(struct udevice *dev)