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From: Pratyush Yadav
To: Chris Packham , Jagan Teki
, Vignesh R , Ryder Lee
, Weijie Gao ,
Chunfeng Yun , GSS_MTK_Uboot_upstream
,
CC: Pratyush Yadav , Takahiro Kuwano
Subject: [PATCH v8 21/28] mtd: spi-nor-core: Do not make invalid quad enable
fatal
Date: Fri, 2 Apr 2021 01:01:26 +0530
Message-ID: <20210401193133.18129-22-p.yadav@ti.com>
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The Micron MT35XU512ABA flash does not support the quad enable bit. But
instead of programming the Quad Enable Require field to 000b ("Device
does not have a QE bit"), it is programmed to 111b ("Reserved").
While this is technically incorrect, it is not reason enough to abort
BFPT parsing. Instead, continue BFPT parsing assuming there is no quad
enable bit present.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index cf0694bca3..2c131bc0f8 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -2100,7 +2100,8 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
break;
#endif
default:
- return -EINVAL;
+ dev_dbg(nor->dev, "BFPT QER reserved value used\n");
+ break;
}
/* Stop here if JESD216 rev B. */