From patchwork Sat Mar 27 02:18:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Green Wan X-Patchwork-Id: 1459093 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4F6jG91yf6z9s1l for ; Sat, 27 Mar 2021 13:19:29 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 81EE182861; Sat, 27 Mar 2021 03:19:11 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id BDBFC827AE; Sat, 27 Mar 2021 03:19:06 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,RDNS_NONE, SPF_HELO_NONE,UNPARSEABLE_RELAY autolearn=no autolearn_force=no version=3.4.2 Received: from transporter.internal.sifive.com (unknown [64.62.193.209]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 49A6682385 for ; Sat, 27 Mar 2021 03:19:03 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=green.wan@sifive.com Received: from gamma15.internal.sifive.com (gamma15.internal.sifive.com [10.14.21.64]) by transporter.internal.sifive.com (Postfix) with ESMTPS id 0B7352047F; Fri, 26 Mar 2021 19:19:02 -0700 (PDT) Received: from localhost (gamma15.internal.sifive.com [local]) by gamma15.internal.sifive.com (OpenSMTPD) with ESMTPA id 11acefe6; Sat, 27 Mar 2021 02:19:01 +0000 (UTC) From: Green Wan To: Cc: Green Wan , Rick Chen , Paul Walmsley , Pragnesh Patel , Sean Anderson , Bin Meng , Simon Glass , Atish Patra , Leo Yu-Chi Liang , Brad Kim , u-boot@lists.denx.de Subject: [RFC PATCH v3 1/2] arch: riscv: cpu: Add callback to init each core Date: Fri, 26 Mar 2021 19:18:29 -0700 Message-Id: <20210327021830.121266-2-green.wan@sifive.com> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20210327021830.121266-1-green.wan@sifive.com> References: <20210327021830.121266-1-green.wan@sifive.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean Add a callback riscv_hart_early_init() to ./arch/riscv/cpu/start.S to allow different riscv hart perform setup code for each hart as early as possible. Since all the harts enter the callback, they must be able to run the same setup. Signed-off-by: Green Wan --- arch/riscv/cpu/cpu.c | 15 +++++++++++++++ arch/riscv/cpu/start.S | 14 ++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index 85592f5bee..c779a477c7 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -140,3 +140,18 @@ int arch_early_init_r(void) { return riscv_cpu_probe(); } + +/** + * riscv_hart_early_init() - A dummy function called by + * ./arch/riscv/cpu/start.S to allow to disable/enable features of each core. + * For example, to turn on or clear chicken bits. + * + * This function is executed by each core after stack is initialized and not + * expect to access gd since gd is not initialized. All operations in this + * function should affect core itself only. In multi-core system, any access + * to common resource or registers outside core should be avoided or need a + * protection for multicore. + */ +__weak void riscv_hart_early_init(void) +{ +} diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 8589509e01..ab73008f23 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -117,6 +117,20 @@ call_board_init_f_0: mv sp, a0 #endif +#if CONFIG_IS_ENABLED(RISCV_MMODE) + /* + * Jump to riscv_hart_early_init() to perform init for each core. Not + * expect to access gd since gd is not initialized. All operations in the + * function should affect core itself only. In multi-core system, any access + * to common resource or registers outside core should be avoided or need a + * protection for multicore. + * + * A dummy implementation is provided in ./arch/riscv/cpu/cpu.c. + */ +call_riscv_hart_early_init: + jal riscv_hart_early_init +#endif + #ifndef CONFIG_XIP /* * Pick hart to initialize global data and run U-Boot. The other harts