| Message ID | 20210323083539.9552-1-green.wan@sifive.com |
|---|---|
| State | RFC |
| Delegated to: | Andes |
| Headers | show |
| Series | [RFC,v2,1/2] arch: riscv: cpu: Add callback to init each core | expand |
On 3/23/21 4:35 AM, Green Wan wrote: > Add a callback riscv_hart_early_init() to ./arch/riscv/cpu/start.S to > allow different riscv hart perform setup code for each hart as early > as possible. Since all the harts enter the calback, they must be able nit: callback > to run the same setup. > > Signed-off-by: Green Wan <green.wan@sifive.com> > --- > arch/riscv/cpu/start.S | 5 +++++ > arch/riscv/lib/spl.c | 4 ++++ > 2 files changed, 9 insertions(+) > > diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S > index 8589509e01..5c7d4da9e2 100644 > --- a/arch/riscv/cpu/start.S > +++ b/arch/riscv/cpu/start.S > @@ -117,6 +117,11 @@ call_board_init_f_0: > mv sp, a0 > #endif > > +#if CONFIG_IS_ENABLED(RISCV_MMODE) > +call_riscv_hart_early_init: > + jal riscv_hart_early_init > +#endif > + > #ifndef CONFIG_XIP > /* > * Pick hart to initialize global data and run U-Boot. The other harts > diff --git a/arch/riscv/lib/spl.c b/arch/riscv/lib/spl.c > index 8baee07bea..e5b1affbfc 100644 > --- a/arch/riscv/lib/spl.c > +++ b/arch/riscv/lib/spl.c > @@ -14,6 +14,10 @@ > > DECLARE_GLOBAL_DATA_PTR; > > +__weak void riscv_hart_early_init(void) > +{ > +} > + Can you add some documentation for what the purpose of this function is and what the limitations are? In particular, this function cannot access gd. --Sean > __weak int spl_board_init_f(void) > { > return 0; >
Hi Green, On Tue, Mar 23, 2021 at 01:35:38AM -0700, Green Wan wrote: > Add a callback riscv_hart_early_init() to ./arch/riscv/cpu/start.S to > allow different riscv hart perform setup code for each hart as early > as possible. Since all the harts enter the calback, they must be able > to run the same setup. > > Signed-off-by: Green Wan <green.wan@sifive.com> > --- > arch/riscv/cpu/start.S | 5 +++++ > arch/riscv/lib/spl.c | 4 ++++ This patch fails to compile for some defconfigs. (CI result: https://dev.azure.com/ycliang-tw/u-boot-riscv/_build/results?buildId=15&view=results) Maybe we should come up with a better place to add this function. Best regards, Leo > 2 files changed, 9 insertions(+) > > diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S > index 8589509e01..5c7d4da9e2 100644 > --- a/arch/riscv/cpu/start.S > +++ b/arch/riscv/cpu/start.S > @@ -117,6 +117,11 @@ call_board_init_f_0: > mv sp, a0 > #endif > > +#if CONFIG_IS_ENABLED(RISCV_MMODE) > +call_riscv_hart_early_init: > + jal riscv_hart_early_init > +#endif > + > #ifndef CONFIG_XIP > /* > * Pick hart to initialize global data and run U-Boot. The other harts > diff --git a/arch/riscv/lib/spl.c b/arch/riscv/lib/spl.c > index 8baee07bea..e5b1affbfc 100644 > --- a/arch/riscv/lib/spl.c > +++ b/arch/riscv/lib/spl.c > @@ -14,6 +14,10 @@ > > DECLARE_GLOBAL_DATA_PTR; > > +__weak void riscv_hart_early_init(void) > +{ > +} > + > __weak int spl_board_init_f(void) > { > return 0;
On 3/25/21 9:22 PM, Leo Liang wrote: > Hi Green, > > On Tue, Mar 23, 2021 at 01:35:38AM -0700, Green Wan wrote: >> Add a callback riscv_hart_early_init() to ./arch/riscv/cpu/start.S to >> allow different riscv hart perform setup code for each hart as early >> as possible. Since all the harts enter the calback, they must be able >> to run the same setup. >> >> Signed-off-by: Green Wan <green.wan@sifive.com> >> --- >> arch/riscv/cpu/start.S | 5 +++++ >> arch/riscv/lib/spl.c | 4 ++++ > > This patch fails to compile for some defconfigs. > (CI result: https://dev.azure.com/ycliang-tw/u-boot-riscv/_build/results?buildId=15&view=results) > > Maybe we should come up with a better place to add this function. arch/riscv/cpu/cpu.c is a good candidate. --Sean > > Best regards, > Leo > >> 2 files changed, 9 insertions(+) >> >> diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S >> index 8589509e01..5c7d4da9e2 100644 >> --- a/arch/riscv/cpu/start.S >> +++ b/arch/riscv/cpu/start.S >> @@ -117,6 +117,11 @@ call_board_init_f_0: >> mv sp, a0 >> #endif >> >> +#if CONFIG_IS_ENABLED(RISCV_MMODE) >> +call_riscv_hart_early_init: >> + jal riscv_hart_early_init >> +#endif >> + >> #ifndef CONFIG_XIP >> /* >> * Pick hart to initialize global data and run U-Boot. The other harts >> diff --git a/arch/riscv/lib/spl.c b/arch/riscv/lib/spl.c >> index 8baee07bea..e5b1affbfc 100644 >> --- a/arch/riscv/lib/spl.c >> +++ b/arch/riscv/lib/spl.c >> @@ -14,6 +14,10 @@ >> >> DECLARE_GLOBAL_DATA_PTR; >> >> +__weak void riscv_hart_early_init(void) >> +{ >> +} >> + >> __weak int spl_board_init_f(void) >> { >> return 0;
On Fri, Mar 26, 2021 at 9:34 AM Sean Anderson <seanga2@gmail.com> wrote: > > On 3/25/21 9:22 PM, Leo Liang wrote: > > Hi Green, > > > > On Tue, Mar 23, 2021 at 01:35:38AM -0700, Green Wan wrote: > >> Add a callback riscv_hart_early_init() to ./arch/riscv/cpu/start.S to > >> allow different riscv hart perform setup code for each hart as early > >> as possible. Since all the harts enter the calback, they must be able > >> to run the same setup. > >> > >> Signed-off-by: Green Wan <green.wan@sifive.com> > >> --- > >> arch/riscv/cpu/start.S | 5 +++++ > >> arch/riscv/lib/spl.c | 4 ++++ > > > > This patch fails to compile for some defconfigs. > > (CI result: https://dev.azure.com/ycliang-tw/u-boot-riscv/_build/results?buildId=15&view=results) > > > > Maybe we should come up with a better place to add this function. > > arch/riscv/cpu/cpu.c is a good candidate. Hi Leo, Thanks for reporting the result. Looks like the test doesn't use "CONFIG_SPL_BUILD"? Thanks to Sean's suggestion, I will move dummy riscv_hart_early_init() from ./arch/riscv/lib/spl.c to ./arch/riscv/cpu/cpu.c to create the next patch. BTW, it's nice if you can share the .config file or CONFIG_* related to CPU? I'd like to check around whether there are other possibilities to break the code building? Thanks, -- Green > > --Sean > > > > > Best regards, > > Leo > > > >> 2 files changed, 9 insertions(+) > >> > >> diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S > >> index 8589509e01..5c7d4da9e2 100644 > >> --- a/arch/riscv/cpu/start.S > >> +++ b/arch/riscv/cpu/start.S > >> @@ -117,6 +117,11 @@ call_board_init_f_0: > >> mv sp, a0 > >> #endif > >> > >> +#if CONFIG_IS_ENABLED(RISCV_MMODE) > >> +call_riscv_hart_early_init: > >> + jal riscv_hart_early_init > >> +#endif > >> + > >> #ifndef CONFIG_XIP > >> /* > >> * Pick hart to initialize global data and run U-Boot. The other harts > >> diff --git a/arch/riscv/lib/spl.c b/arch/riscv/lib/spl.c > >> index 8baee07bea..e5b1affbfc 100644 > >> --- a/arch/riscv/lib/spl.c > >> +++ b/arch/riscv/lib/spl.c > >> @@ -14,6 +14,10 @@ > >> > >> DECLARE_GLOBAL_DATA_PTR; > >> > >> +__weak void riscv_hart_early_init(void) > >> +{ > >> +} > >> + > >> __weak int spl_board_init_f(void) > >> { > >> return 0; >
On Fri, Mar 26, 2021 at 05:03:54PM +0800, Green Wan wrote: > On Fri, Mar 26, 2021 at 9:34 AM Sean Anderson <seanga2@gmail.com> wrote: > > > > On 3/25/21 9:22 PM, Leo Liang wrote: > > > Hi Green, > > > > > > On Tue, Mar 23, 2021 at 01:35:38AM -0700, Green Wan wrote: > > >> Add a callback riscv_hart_early_init() to ./arch/riscv/cpu/start.S to > > >> allow different riscv hart perform setup code for each hart as early > > >> as possible. Since all the harts enter the calback, they must be able > > >> to run the same setup. > > >> > > >> Signed-off-by: Green Wan <green.wan@sifive.com> > > >> --- > > >> arch/riscv/cpu/start.S | 5 +++++ > > >> arch/riscv/lib/spl.c | 4 ++++ > > > > > > This patch fails to compile for some defconfigs. > > > (CI result: https://dev.azure.com/ycliang-tw/u-boot-riscv/_build/results?buildId=15&view=results) > > > > > > Maybe we should come up with a better place to add this function. > > > > arch/riscv/cpu/cpu.c is a good candidate. > > Hi Leo, > > Thanks for reporting the result. Looks like the test doesn't use > "CONFIG_SPL_BUILD"? Thanks to Sean's suggestion, I will move dummy > riscv_hart_early_init() from ./arch/riscv/lib/spl.c to > ./arch/riscv/cpu/cpu.c to create the next patch. > > BTW, it's nice if you can share the .config file or CONFIG_* related > to CPU? I'd like to check around whether there are other possibilities > to break the code building? Thanks, > > -- Green > Hi Green, Sorry for the late reply. It seems that this v2 patch would fail to compile with but not limited to the following configs. qemu-riscv[32|64]_defconfig, ae350_rv[32|64]_defconfig... The v3 patch seems to fix the compile error, thanks! Best regards, Leo > > > > > --Sean > > > > > > > > Best regards, > > > Leo > > > > > >> 2 files changed, 9 insertions(+) > > >> > > >> diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S > > >> index 8589509e01..5c7d4da9e2 100644 > > >> --- a/arch/riscv/cpu/start.S > > >> +++ b/arch/riscv/cpu/start.S > > >> @@ -117,6 +117,11 @@ call_board_init_f_0: > > >> mv sp, a0 > > >> #endif > > >> > > >> +#if CONFIG_IS_ENABLED(RISCV_MMODE) > > >> +call_riscv_hart_early_init: > > >> + jal riscv_hart_early_init > > >> +#endif > > >> + > > >> #ifndef CONFIG_XIP > > >> /* > > >> * Pick hart to initialize global data and run U-Boot. The other harts > > >> diff --git a/arch/riscv/lib/spl.c b/arch/riscv/lib/spl.c > > >> index 8baee07bea..e5b1affbfc 100644 > > >> --- a/arch/riscv/lib/spl.c > > >> +++ b/arch/riscv/lib/spl.c > > >> @@ -14,6 +14,10 @@ > > >> > > >> DECLARE_GLOBAL_DATA_PTR; > > >> > > >> +__weak void riscv_hart_early_init(void) > > >> +{ > > >> +} > > >> + > > >> __weak int spl_board_init_f(void) > > >> { > > >> return 0; > >
Oaky, thanks for sharing the defconfig info. - Green Leo Liang <ycliang@andestech.com>於 2021年3月29日 週一，上午10:24寫道： > On Fri, Mar 26, 2021 at 05:03:54PM +0800, Green Wan wrote: > > On Fri, Mar 26, 2021 at 9:34 AM Sean Anderson <seanga2@gmail.com> wrote: > > > > > > On 3/25/21 9:22 PM, Leo Liang wrote: > > > > Hi Green, > > > > > > > > On Tue, Mar 23, 2021 at 01:35:38AM -0700, Green Wan wrote: > > > >> Add a callback riscv_hart_early_init() to ./arch/riscv/cpu/start.S > to > > > >> allow different riscv hart perform setup code for each hart as early > > > >> as possible. Since all the harts enter the calback, they must be > able > > > >> to run the same setup. > > > >> > > > >> Signed-off-by: Green Wan <green.wan@sifive.com> > > > >> --- > > > >> arch/riscv/cpu/start.S | 5 +++++ > > > >> arch/riscv/lib/spl.c | 4 ++++ > > > > > > > > This patch fails to compile for some defconfigs. > > > > (CI result: > https://dev.azure.com/ycliang-tw/u-boot-riscv/_build/results?buildId=15&view=results > ) > > > > > > > > Maybe we should come up with a better place to add this function. > > > > > > arch/riscv/cpu/cpu.c is a good candidate. > > > > Hi Leo, > > > > Thanks for reporting the result. Looks like the test doesn't use > > "CONFIG_SPL_BUILD"? Thanks to Sean's suggestion, I will move dummy > > riscv_hart_early_init() from ./arch/riscv/lib/spl.c to > > ./arch/riscv/cpu/cpu.c to create the next patch. > > > > BTW, it's nice if you can share the .config file or CONFIG_* related > > to CPU? I'd like to check around whether there are other possibilities > > to break the code building? Thanks, > > > > -- Green > > > Hi Green, > > Sorry for the late reply. > It seems that this v2 patch would fail to compile with but not limited to > the following configs. > qemu-riscv[32|64]_defconfig, ae350_rv[32|64]_defconfig... > > The v3 patch seems to fix the compile error, thanks! > > Best regards, > Leo > > > > > > > > --Sean > > > > > > > > > > > Best regards, > > > > Leo > > > > > > > >> 2 files changed, 9 insertions(+) > > > >> > > > >> diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S > > > >> index 8589509e01..5c7d4da9e2 100644 > > > >> --- a/arch/riscv/cpu/start.S > > > >> +++ b/arch/riscv/cpu/start.S > > > >> @@ -117,6 +117,11 @@ call_board_init_f_0: > > > >> mv sp, a0 > > > >> #endif > > > >> > > > >> +#if CONFIG_IS_ENABLED(RISCV_MMODE) > > > >> +call_riscv_hart_early_init: > > > >> + jal riscv_hart_early_init > > > >> +#endif > > > >> + > > > >> #ifndef CONFIG_XIP > > > >> /* > > > >> * Pick hart to initialize global data and run U-Boot. The > other harts > > > >> diff --git a/arch/riscv/lib/spl.c b/arch/riscv/lib/spl.c > > > >> index 8baee07bea..e5b1affbfc 100644 > > > >> --- a/arch/riscv/lib/spl.c > > > >> +++ b/arch/riscv/lib/spl.c > > > >> @@ -14,6 +14,10 @@ > > > >> > > > >> DECLARE_GLOBAL_DATA_PTR; > > > >> > > > >> +__weak void riscv_hart_early_init(void) > > > >> +{ > > > >> +} > > > >> + > > > >> __weak int spl_board_init_f(void) > > > >> { > > > >> return 0; > > > >
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 8589509e01..5c7d4da9e2 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -117,6 +117,11 @@ call_board_init_f_0: mv sp, a0 #endif +#if CONFIG_IS_ENABLED(RISCV_MMODE) +call_riscv_hart_early_init: + jal riscv_hart_early_init +#endif + #ifndef CONFIG_XIP /* * Pick hart to initialize global data and run U-Boot. The other harts diff --git a/arch/riscv/lib/spl.c b/arch/riscv/lib/spl.c index 8baee07bea..e5b1affbfc 100644 --- a/arch/riscv/lib/spl.c +++ b/arch/riscv/lib/spl.c @@ -14,6 +14,10 @@ DECLARE_GLOBAL_DATA_PTR; +__weak void riscv_hart_early_init(void) +{ +} + __weak int spl_board_init_f(void) { return 0;
Add a callback riscv_hart_early_init() to ./arch/riscv/cpu/start.S to allow different riscv hart perform setup code for each hart as early as possible. Since all the harts enter the calback, they must be able to run the same setup. Signed-off-by: Green Wan <green.wan@sifive.com> --- arch/riscv/cpu/start.S | 5 +++++ arch/riscv/lib/spl.c | 4 ++++ 2 files changed, 9 insertions(+)