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Mon, 4 Jan 2021 08:03:13 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=xypron.glpk@gmx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1609743788; bh=/dgMJc8vCs39OuxxYmjL0XoojBbp5zr+2xrV5WlgHIU=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=bz+Hlrc6j5EoQ1es1TjtPjNc63St4TL+tOyxL3urCuL8qLjlpUHstIX53dVHxikgY +j1QhYGZjBCfQVPXE95ZF+1dJBSyg1McQL4RrLHJ0n2ns0YrVo6mAAi+D58i74VAGG QVbYTnsht/cXCXQgDrmDjvOSwkA/JM44rb7ykpZE= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from LT02.fritz.box ([62.143.246.89]) by mail.gmx.com (mrgmx104 [212.227.17.174]) with ESMTPSA (Nemesis) id 1McYCb-1kQXqL2ODN-00d27d; Mon, 04 Jan 2021 08:03:08 +0100 From: Heinrich Schuchardt To: Simon Glass Cc: Lokesh Vutla , Bin Meng , Vignesh Raghavendra , Grygorii Strashko , Sean Anderson , u-boot@lists.denx.de, Heinrich Schuchardt Subject: [PATCH 1/5] ram: k3-j721e: rename BIT_MASK() Date: Mon, 4 Jan 2021 08:02:52 +0100 Message-Id: <20210104070256.260002-2-xypron.glpk@gmx.de> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210104070256.260002-1-xypron.glpk@gmx.de> References: <20210104070256.260002-1-xypron.glpk@gmx.de> MIME-Version: 1.0 X-Provags-ID: V03:K1:cm8r2FseohSGhAeaWHee/mvl0ZeagPFD+D1dIWKBO890A1Lo2J/ 50OIvP+fI3a9jlPWYVjb2iXKUSao9o8mJD8bxwcscGT9DPNrERoDDqCKbonyE0iHq/45l57 58k6/Az+rJuRwcGvnZtsqklP/FHBipzmXWR+ZG/jTXdD2oTqAJu4x/RahaDR1OZBOie1+nb nI870F/KOYaHKm201AzPQ== X-UI-Out-Filterresults: notjunk:1;V03:K0:JUAG6cuP53I=:1o+lmiC0kTi6eyoyL6XXgh UdqNoAU9U/6XpCG6aChObg9kuTAZef1ASH6UaVb0i9+jmFcPt9yCbDxh2XdEws19c3iMwEEE3 FjXS3Oe3gIyOTPSemj+eaNBi4fMgvKsiThpm4movoVdoPQ1yN2K4wEFdMF6hgeVsoo+pyNFPF 48uzWsiqLDBy2wb+/rBi++Kbs95tHiSvF+6CqAsIntR5BSe50WtThX+VvUzwTmF9RebnFbDgf bRAoa5be1+0dPTkxxs7Q0YdUZe4DtEq7HBq+7yvix2aZ9ufOt3KhOD8C0ZgHMFy8CNTOGQoyN fU6U2rwr0SKAeTYj3JTRRAAxUjE/cnz684bm1Tblj0zha3ZfSY+BGRfyfLzPm53h8Yy/H3Amu R1BbT5zfN32s/9Z1ZZbb5fMK13Cu0sW+r7WAxYpZjyn6HuaqnPoOP0XK4p1hulUUOlHnVt021 r8SvoNSPl28IeRF4yOeRFvGbQY8NXTHKuVO3QZ2IvWssjr9G16lRK10+uYa4m3JB0/f2fr2+S keMeN0MaWMTF6bftqY7RjzL/YqA8hcgFSpRUUonpTijt3hf1OlQJMRECAQWop9egc8j1Vd3HN 0gDtuYHZfzfbNA1mFfzwoe3CuBKAOXwaUrsyKKPCsw6hA+RWJeq5YE+IG0xtS/HFrzNCzFRCP jH3xcfbcRYsjdByAwC1kKCAcjd2yNvkxi7S1kCSFZbD7qQSQdaOVSMkFjhBJh0QV/6xTbRNUZ PWS5dlojtDZVkibVU72L4FwgdKHpZoAOOP7D6TzasR7l92mRT/VHxSCu1aGpV/KNYYpe7BGvT xUrXWTf3dtSiZrBAmz0UCpKSVpn/6iVOIxKjnYdJSF2Lqc0C5OuZFtj3uonaS7pnj3g2gH6ym 62ZaQQt9pv9K1LtPCCew== X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean The macro BIT_MASK is already defined in include/linux/bitops.h. To avoid name collisions rename BIT_MASK() in drivers/ram/k3-j721e/lpddr4_private.h to LPDDR4_BIT_MASK(). Remove superfluous parantheses. Remove superfluous comparison to 0. Signed-off-by: Heinrich Schuchardt Reviewed-by: Simon Glass --- drivers/ram/k3-j721e/lpddr4.c | 14 +++++++------- drivers/ram/k3-j721e/lpddr4_private.h | 20 ++++++++++++-------- 2 files changed, 19 insertions(+), 15 deletions(-) -- 2.29.2 diff --git a/drivers/ram/k3-j721e/lpddr4.c b/drivers/ram/k3-j721e/lpddr4.c index fc80fb1e2c..68043d7cb6 100644 --- a/drivers/ram/k3-j721e/lpddr4.c +++ b/drivers/ram/k3-j721e/lpddr4.c @@ -719,7 +719,7 @@ uint32_t lpddr4_checkctlinterrupt(const lpddr4_privatedata * pd, /* MISRA compliance (Shifting operation) check */ if (fieldshift < WORD_SHIFT) { - if (((ctlirqstatus >> fieldshift) & BIT_MASK) > 0U) { + if ((ctlirqstatus >> fieldshift) & LPDDR4_BIT_MASK) { *irqstatus = true; } else { *irqstatus = false; @@ -746,11 +746,11 @@ uint32_t lpddr4_ackctlinterrupt(const lpddr4_privatedata * pd, if (localinterrupt > WORD_SHIFT) { localinterrupt = (localinterrupt - (uint32_t) WORD_SHIFT); - regval = ((uint32_t) BIT_MASK << localinterrupt); + regval = (uint32_t)LPDDR4_BIT_MASK << localinterrupt; CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_1__REG), regval); } else { - regval = ((uint32_t) BIT_MASK << localinterrupt); + regval = (uint32_t)LPDDR4_BIT_MASK << localinterrupt; CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_0__REG), regval); } @@ -823,7 +823,7 @@ uint32_t lpddr4_checkphyindepinterrupt(const lpddr4_privatedata * pd, phyindepirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INT_STATUS__REG)); *irqstatus = - (((phyindepirqstatus >> (uint32_t) intr) & BIT_MASK) > 0U); + !!((phyindepirqstatus >> (uint32_t)intr) & LPDDR4_BIT_MASK); } return result; } @@ -841,7 +841,7 @@ uint32_t lpddr4_ackphyindepinterrupt(const lpddr4_privatedata * pd, lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase; /* Write 1 to the requested bit to ACk the interrupt */ - regval = ((uint32_t) BIT_MASK << ui32shiftinterrupt); + regval = (uint32_t)LPDDR4_BIT_MASK << ui32shiftinterrupt; CPS_REG_WRITE(&(ctlregbase->LPDDR4__PI_INT_ACK__REG), regval); } @@ -894,7 +894,7 @@ static void lpddr4_checkwrlvlerror(lpddr4_ctlregs * ctlregbase, (volatile uint32_t *)(&(ctlregbase->LPDDR4__PHY_WRLVL_ERROR_OBS_0__REG)); /* PHY_WRLVL_ERROR_OBS_X[1:0] should be zero */ - errbitmask = (BIT_MASK << 1) | (BIT_MASK); + errbitmask = (LPDDR4_BIT_MASK << 1) | LPDDR4_BIT_MASK; for (snum = 0U; snum < DSLICE_NUM; snum++) { regval = CPS_REG_READ(regaddress); if ((regval & errbitmask) != 0U) { @@ -1054,7 +1054,7 @@ static void lpddr4_seterrors(lpddr4_ctlregs * ctlregbase, lpddr4_debuginfo * debuginfo, bool * errfoundptr) { - uint32_t errbitmask = (BIT_MASK << 0x1U) | (BIT_MASK); + uint32_t errbitmask = (LPDDR4_BIT_MASK << 0x1U) | LPDDR4_BIT_MASK; /* Check PLL observation registers for PLL lock errors */ debuginfo->pllerror = diff --git a/drivers/ram/k3-j721e/lpddr4_private.h b/drivers/ram/k3-j721e/lpddr4_private.h index 42c923464a..3d5017ea47 100644 --- a/drivers/ram/k3-j721e/lpddr4_private.h +++ b/drivers/ram/k3-j721e/lpddr4_private.h @@ -14,9 +14,9 @@ #define VERSION_0 (0x54d5da40U) #define VERSION_1 (0xc1865a1U) -#define BIT_MASK (0x1U) -#define BYTE_MASK (0xffU) -#define NIBBLE_MASK (0xfU) +#define LPDDR4_BIT_MASK (0x1U) +#define BYTE_MASK (0xffU) +#define NIBBLE_MASK (0xfU) #define WORD_SHIFT (32U) #define WORD_MASK (0xffffffffU) @@ -46,11 +46,15 @@ #define IO_CALIB_DONE ((uint32_t)0x1U << 23U) #define IO_CALIB_FIELD ((uint32_t)NIBBLE_MASK << 28U) #define IO_CALIB_STATE ((uint32_t)0xBU << 28U) -#define RX_CAL_DONE ((uint32_t)BIT_MASK << 4U) -#define CA_TRAIN_RL (((uint32_t)BIT_MASK << 5U) | ((uint32_t)BIT_MASK << 4U)) +#define RX_CAL_DONE ((uint32_t)LPDDR4_BIT_MASK << 4U) +#define CA_TRAIN_RL (((uint32_t)LPDDR4_BIT_MASK << 5U) | \ + ((uint32_t)LPDDR4_BIT_MASK << 4U)) #define WR_LVL_STATE (((uint32_t)NIBBLE_MASK) << 13U) -#define GATE_LVL_ERROR_FIELDS (((uint32_t)BIT_MASK << 7U) | ((uint32_t)BIT_MASK << 6U)) -#define READ_LVL_ERROR_FIELDS ((((uint32_t)NIBBLE_MASK) << 28U) | (((uint32_t)BYTE_MASK) << 16U)) -#define DQ_LVL_STATUS (((uint32_t)BIT_MASK << 26U) | (((uint32_t)BYTE_MASK) << 18U)) +#define GATE_LVL_ERROR_FIELDS (((uint32_t)LPDDR4_BIT_MASK << 7U) | \ + ((uint32_t)LPDDR4_BIT_MASK << 6U)) +#define READ_LVL_ERROR_FIELDS ((((uint32_t)NIBBLE_MASK) << 28U) | \ + (((uint32_t)BYTE_MASK) << 16U)) +#define DQ_LVL_STATUS (((uint32_t)LPDDR4_BIT_MASK << 26U) | \ + (((uint32_t)BYTE_MASK) << 18U)) #endif /* LPDDR4_PRIV_H */