| Message ID | 20210103092633.36226-11-jernej.skrabec@siol.net |
|---|---|
| State | Superseded |
| Delegated to: | Andre Przywara |
| Headers | show |
| Series | sunxi: Introduce H616 support | expand |
On 1/3/21 3:26 AM, Jernej Skrabec wrote: > This port is needed for communication with PMIC. SPL uses it to set DRAM > voltage on H616 boards. > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> > --- > arch/arm/include/asm/arch-sunxi/gpio.h | 1 + > board/sunxi/board.c | 4 ++++ > 2 files changed, 5 insertions(+) > > diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h > index cdb7dbd5b8e5..de77bf638e21 100644 > --- a/arch/arm/include/asm/arch-sunxi/gpio.h > +++ b/arch/arm/include/asm/arch-sunxi/gpio.h > @@ -220,6 +220,7 @@ enum sunxi_gpio_number { > #define SUN8I_A23_GPL_R_TWI 3 > #define SUN8I_GPL_R_UART 2 > #define SUN50I_GPL_R_TWI 2 > +#define SUN50I_H616_GPL_R_TWI 3 The fact that I2C is at function 3 makes me suspicious that there is RSB at function 2. Have you checked if that is the case? Either way: Reviewed-by: Samuel Holland <samuel@sholland.org> > #define SUN9I_GPN_R_RSB 3 > > diff --git a/board/sunxi/board.c b/board/sunxi/board.c > index 54ff9bc92396..727e8320318f 100644 > --- a/board/sunxi/board.c > +++ b/board/sunxi/board.c > @@ -196,6 +196,10 @@ void i2c_init_board(void) > clock_twi_onoff(5, 1); > sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI); > sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI); > +#elif CONFIG_MACH_SUN50I_H616 > + clock_twi_onoff(5, 1); > + sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN50I_H616_GPL_R_TWI); > + sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN50I_H616_GPL_R_TWI); > #else > clock_twi_onoff(5, 1); > sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI); >
Dne ponedeljek, 04. januar 2021 ob 03:33:12 CET je Samuel Holland napisal(a): > On 1/3/21 3:26 AM, Jernej Skrabec wrote: > > This port is needed for communication with PMIC. SPL uses it to set DRAM > > voltage on H616 boards. > > > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> > > --- > > > > arch/arm/include/asm/arch-sunxi/gpio.h | 1 + > > board/sunxi/board.c | 4 ++++ > > 2 files changed, 5 insertions(+) > > > > diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h > > b/arch/arm/include/asm/arch-sunxi/gpio.h index cdb7dbd5b8e5..de77bf638e21 > > 100644 > > --- a/arch/arm/include/asm/arch-sunxi/gpio.h > > +++ b/arch/arm/include/asm/arch-sunxi/gpio.h > > @@ -220,6 +220,7 @@ enum sunxi_gpio_number { > > > > #define SUN8I_A23_GPL_R_TWI 3 > > #define SUN8I_GPL_R_UART 2 > > #define SUN50I_GPL_R_TWI 2 > > > > +#define SUN50I_H616_GPL_R_TWI 3 > > The fact that I2C is at function 3 makes me suspicious that there is RSB > at function 2. Have you checked if that is the case? BSP Linux pinctrl has function 2 s_rsb0, so yes, that should be the case. However, it doesn't have RSB DT node anywhere. Datasheet mentions RSB only in CCU diagram, so no details anywhere. I didn't test it. Best regards, Jernej > > Either way: > > Reviewed-by: Samuel Holland <samuel@sholland.org> > > > #define SUN9I_GPN_R_RSB 3 > > > > diff --git a/board/sunxi/board.c b/board/sunxi/board.c > > index 54ff9bc92396..727e8320318f 100644 > > --- a/board/sunxi/board.c > > +++ b/board/sunxi/board.c > > @@ -196,6 +196,10 @@ void i2c_init_board(void) > > > > clock_twi_onoff(5, 1); > > sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI); > > sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI); > > > > +#elif CONFIG_MACH_SUN50I_H616 > > + clock_twi_onoff(5, 1); > > + sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN50I_H616_GPL_R_TWI); > > + sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN50I_H616_GPL_R_TWI); > > > > #else > > > > clock_twi_onoff(5, 1); > > sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index cdb7dbd5b8e5..de77bf638e21 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -220,6 +220,7 @@ enum sunxi_gpio_number { #define SUN8I_A23_GPL_R_TWI 3 #define SUN8I_GPL_R_UART 2 #define SUN50I_GPL_R_TWI 2 +#define SUN50I_H616_GPL_R_TWI 3 #define SUN9I_GPN_R_RSB 3 diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 54ff9bc92396..727e8320318f 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -196,6 +196,10 @@ void i2c_init_board(void) clock_twi_onoff(5, 1); sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI); sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI); +#elif CONFIG_MACH_SUN50I_H616 + clock_twi_onoff(5, 1); + sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN50I_H616_GPL_R_TWI); + sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN50I_H616_GPL_R_TWI); #else clock_twi_onoff(5, 1); sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
This port is needed for communication with PMIC. SPL uses it to set DRAM voltage on H616 boards. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> --- arch/arm/include/asm/arch-sunxi/gpio.h | 1 + board/sunxi/board.c | 4 ++++ 2 files changed, 5 insertions(+)