From patchwork Fri Oct 16 03:13:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yangbo Lu X-Patchwork-Id: 1383029 X-Patchwork-Delegate: van.freenix@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nxp.com Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4CCBLB3mfgz9sTD for ; Fri, 16 Oct 2020 14:22:58 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id B557B823B6; Fri, 16 Oct 2020 05:22:35 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=nxp.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id F0D5081BD2; Fri, 16 Oct 2020 05:22:32 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 4A05081BD2 for ; Fri, 16 Oct 2020 05:22:29 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=yangbo.lu@nxp.com Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 19C762006C6; Fri, 16 Oct 2020 05:22:29 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 6D46E2008E6; Fri, 16 Oct 2020 05:22:27 +0200 (CEST) Received: from localhost.localdomain (mega.ap.freescale.net [10.192.208.232]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 09787402D9; Fri, 16 Oct 2020 05:22:24 +0200 (CEST) From: Yangbo Lu To: u-boot@lists.denx.de, Peng Fan Cc: Yangbo Lu Subject: [PATCH 2/2] mmc: fsl_esdhc: make sure delay chain locked for HS400 Date: Fri, 16 Oct 2020 11:13:32 +0800 Message-Id: <20201016031332.21456-3-yangbo.lu@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201016031332.21456-1-yangbo.lu@nxp.com> References: <20201016031332.21456-1-yangbo.lu@nxp.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean For eMMC HS400 mode, the DLL reset is a required step for mmc rescan. This step has not been documented in reference manual, but the RM will be fixed sooner or later. This patch is to add the step of DLL reset, and make sure delay chain locked for HS400. Fixes: db8f93672b42 ("mmc: fsl_esdhc: support eMMC HS400 mode") Signed-off-by: Yangbo Lu Reviewed-by: Jaehoon Chung --- drivers/mmc/fsl_esdhc.c | 28 +++++++++++++++++++++++++--- include/fsl_esdhc.h | 4 ++++ 2 files changed, 29 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 68130ee..a18316e 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -70,7 +70,9 @@ struct fsl_esdhc { uint sdtimingctl; /* SD timing control register */ char reserved8[20]; /* reserved */ uint dllcfg0; /* DLL config 0 register */ - char reserved9[680]; /* reserved */ + char reserved9[12]; /* reserved */ + uint dllstat0; /* DLL status 0 register */ + char reserved10[664];/* reserved */ uint esdhcctl; /* eSDHC control register */ }; @@ -617,9 +619,11 @@ static void esdhc_exit_hs400(struct fsl_esdhc_priv *priv) esdhc_tuning_block_enable(priv, false); } -static void esdhc_set_timing(struct fsl_esdhc_priv *priv, enum bus_mode mode) +static int esdhc_set_timing(struct fsl_esdhc_priv *priv, enum bus_mode mode) { struct fsl_esdhc *regs = priv->esdhc_regs; + ulong start; + u32 val; /* Exit HS400 mode before setting any other mode */ if (esdhc_read32(®s->tbctl) & HS400_MODE && @@ -640,17 +644,33 @@ static void esdhc_set_timing(struct fsl_esdhc_priv *priv, enum bus_mode mode) esdhc_setbits32(®s->dllcfg0, DLL_FREQ_SEL); esdhc_setbits32(®s->dllcfg0, DLL_ENABLE); + + esdhc_setbits32(®s->dllcfg0, DLL_RESET); + udelay(1); + esdhc_clrbits32(®s->dllcfg0, DLL_RESET); + + start = get_timer(0); + val = DLL_STS_SLV_LOCK; + while (!(esdhc_read32(®s->dllstat0) & val)) { + if (get_timer(start) > 1000) { + printf("fsl_esdhc: delay chain lock timeout\n"); + return -ETIMEDOUT; + } + } + esdhc_setbits32(®s->tbctl, HS400_WNDW_ADJUST); esdhc_clock_control(priv, false); esdhc_flush_async_fifo(priv); } esdhc_clock_control(priv, true); + return 0; } static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) { struct fsl_esdhc *regs = priv->esdhc_regs; + int ret; if (priv->is_sdhc_per_clk) { /* Select to use peripheral clock */ @@ -667,7 +687,9 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) set_sysctl(priv, mmc, mmc->clock); /* Set timing */ - esdhc_set_timing(priv, mmc->selected_mode); + ret = esdhc_set_timing(priv, mmc->selected_mode); + if (ret) + return ret; /* Set the bus width */ esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8); diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index e6f1c75..850a304 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -187,8 +187,12 @@ /* DLL config 0 register */ #define DLL_ENABLE 0x80000000 +#define DLL_RESET 0x40000000 #define DLL_FREQ_SEL 0x08000000 +/* DLL status 0 register */ +#define DLL_STS_SLV_LOCK 0x08000000 + #define MAX_TUNING_LOOP 40 #define HOSTVER_VENDOR(x) (((x) >> 8) & 0xff)