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Thu, 20 Aug 2020 10:58:35 +0000 (UTC) From: Frank Wunderlich To: u-boot@lists.denx.de Cc: Frank Wunderlich , GSS_MTK_Uboot_upstream@mediatek.com, chunfeng.yun@mediatek.com, sam.shih@mediatek.com Subject: [PATCH v4 04/11] reset: add basic reset controller for pciesys Date: Thu, 20 Aug 2020 12:58:19 +0200 Message-Id: <20200820105826.6229-5-linux@fw-web.de> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200820105826.6229-1-linux@fw-web.de> References: <20200820105826.6229-1-linux@fw-web.de> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean From: Frank Wunderlich bind reset controller to pciesys Signed-off-by: Frank Wunderlich --- drivers/clk/mediatek/clk-mt7622.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index bd86b5b974..a1a35f72a3 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -594,6 +594,19 @@ static int mt7622_pciesys_probe(struct udevice *dev) return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, pcie_cgs); } +static int mt7622_pciesys_bind(struct udevice *dev) +{ + int ret = 0; + + if (IS_ENABLED(CONFIG_RESET_MEDIATEK)) { + ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1); + if (ret) + debug("Warning: failed to bind reset controller\n"); + } + + return ret; +} + static int mt7622_ethsys_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, eth_cgs); @@ -710,6 +723,7 @@ U_BOOT_DRIVER(mtk_clk_pciesys) = { .id = UCLASS_CLK, .of_match = mt7622_pciesys_compat, .probe = mt7622_pciesys_probe, + .bind = mt7622_pciesys_bind, .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), .ops = &mtk_clk_gate_ops, };