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Tue, 18 Aug 2020 14:10:22 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 18 Aug 2020 14:10:22 -0500 Received: from fllv0103.dal.design.ti.com (fllv0103.dal.design.ti.com [10.247.120.73]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 07IJAME0114050; Tue, 18 Aug 2020 14:10:22 -0500 Received: from localhost ([10.250.32.29]) by fllv0103.dal.design.ti.com (8.14.7/8.14.7) with ESMTP id 07IJAL0I060585; Tue, 18 Aug 2020 14:10:21 -0500 From: Suman Anna To: Lokesh Vutla CC: , Suman Anna Subject: [PATCH 1/3] env: ti: j721e-evm: Update R5 SPL rproc env variables for J7200 Date: Tue, 18 Aug 2020 14:09:43 -0500 Message-ID: <20200818190945.8966-2-s-anna@ti.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200818190945.8966-1-s-anna@ti.com> References: <20200818190945.8966-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean The R5 SPL on J7200 SoCs will be limited to booting just the MCU R5FSS0 R5F core in LockStep-mode at present, so add the two required environment variables 'addr_mcur5f0_0load' and 'name_mcur5f0_0fw' that are needed by the R5 SPL early-boot logic. The firmware name used is also different from that on J721E SoCs. Signed-off-by: Suman Anna --- include/configs/j721e_evm.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h index dc06de234154..5e6e6f81694b 100644 --- a/include/configs/j721e_evm.h +++ b/include/configs/j721e_evm.h @@ -82,11 +82,17 @@ "name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" #ifdef CONFIG_SYS_K3_SPL_ATF +#if defined(CONFIG_TARGET_J721E_R5_EVM) #define EXTRA_ENV_R5_SPL_RPROC_FW_ARGS_MMC \ "addr_mainr5f0_0load=0x88000000\0" \ "name_mainr5f0_0fw=/lib/firmware/j7-main-r5f0_0-fw\0" \ "addr_mcur5f0_0load=0x89000000\0" \ "name_mcur5f0_0fw=/lib/firmware/j7-mcu-r5f0_0-fw\0" +#elif defined(CONFIG_TARGET_J7200_R5_EVM) +#define EXTRA_ENV_R5_SPL_RPROC_FW_ARGS_MMC \ + "addr_mcur5f0_0load=0x89000000\0" \ + "name_mcur5f0_0fw=/lib/firmware/j7200-mcu-r5f0_0-fw\0" +#endif /* CONFIG_TARGET_J721E_R5_EVM */ #else #define EXTRA_ENV_R5_SPL_RPROC_FW_ARGS_MMC "" #endif /* CONFIG_SYS_K3_SPL_ATF */