From patchwork Tue Jun 30 05:57:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 1319551 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=b3cft/8s; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 49wtwW59kZz9sR4 for ; Tue, 30 Jun 2020 15:59:23 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 02CD7816B4; Tue, 30 Jun 2020 07:59:12 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="b3cft/8s"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 070D681525; Tue, 30 Jun 2020 07:58:44 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 6B04D80927 for ; Tue, 30 Jun 2020 07:58:38 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=vigneshr@ti.com Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 05U5wbvu119301 for ; Tue, 30 Jun 2020 00:58:37 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1593496717; bh=Sg073yqPacG4lYv6DKDaO+xgmBDLOTKS7eIP4JcwFps=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=b3cft/8sNWWshPspEb6i5S8X6I4hACDl6IYVNOyOw4rweubDioWo0Yrz1ioXDevCa /5e6y5WJRakaqApf9iHyhVmo/RBRgwEsCL2CuzZdmlHLTICTOWFnzzRbTqE3MyG22c IGt/N8rP1bdMpcHVei1uR9P85TaNQyZKgAzcmsto= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 05U5wbQI079268 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL) for ; Tue, 30 Jun 2020 00:58:37 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 30 Jun 2020 00:58:36 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 30 Jun 2020 00:58:36 -0500 Received: from ula0132425.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 05U5wTUL093219; Tue, 30 Jun 2020 00:58:35 -0500 From: Vignesh Raghavendra To: Lokesh Vutla CC: Vignesh Raghavendra , , Subject: [PATCH v2 2/3] dma: ti: k3-udma: Update driver to use static endpoint Data Date: Tue, 30 Jun 2020 11:27:49 +0530 Message-ID: <20200630055750.4538-3-vigneshr@ti.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200630055750.4538-1-vigneshr@ti.com> References: <20200630055750.4538-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean Update driver to use static PSIL endpoint Data instead of DT. This will allow DT bindings to be in sync with kernel's DT. Note that this patch breaks networking and OSPI boot as driver changes are not backward compatible with existing DT. Subsequent commit will update the DT to make it compatible with updated driver. Signed-off-by: Vignesh Raghavendra Reviewed-by: Grygorii Strashko --- drivers/dma/ti/Kconfig | 1 + drivers/dma/ti/k3-udma.c | 145 +++++++++++++++++++++++++++------------ 2 files changed, 103 insertions(+), 43 deletions(-) diff --git a/drivers/dma/ti/Kconfig b/drivers/dma/ti/Kconfig index 9d7a1efb2b..9cbd5f334d 100644 --- a/drivers/dma/ti/Kconfig +++ b/drivers/dma/ti/Kconfig @@ -8,6 +8,7 @@ config TI_K3_NAVSS_UDMA select DMA select TI_K3_NAVSS_RINGACC select TI_K3_NAVSS_PSILCFG + select TI_K3_PSIL default n help Support for UDMA used in K3 devices. diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index 2ce16c8e27..5fc8692e19 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include #include @@ -31,6 +30,7 @@ #include #include "k3-udma-hwdef.h" +#include "k3-psil-priv.h" #if BITS_PER_LONG == 64 #define RINGACC_RING_USE_PROXY (0) @@ -69,6 +69,21 @@ struct udma_rchan { struct k3_nav_ring *r_ring; /* Receive ring*/ }; +#define UDMA_FLAG_PDMA_ACC32 BIT(0) +#define UDMA_FLAG_PDMA_BURST BIT(1) +#define UDMA_FLAG_TDTYPE BIT(2) + +struct udma_match_data { + u32 psil_base; + bool enable_memcpy_support; + u32 flags; + u32 statictr_z_mask; + u32 rchan_oes_offset; + + u8 tpl_levels; + u32 level_start_idx[]; +}; + struct udma_rflow { int id; }; @@ -114,6 +129,8 @@ struct udma_dev { struct udma_rchan *rchans; struct udma_rflow *rflows; + struct udma_match_data *match_data; + struct udma_chan *channels; u32 psil_base; @@ -1293,12 +1310,8 @@ static int udma_probe(struct udevice *dev) if (IS_ERR(ud->ringacc)) return PTR_ERR(ud->ringacc); - ud->psil_base = dev_read_u32_default(dev, "ti,psil-base", 0); - if (!ud->psil_base) { - dev_info(dev, - "Missing ti,psil-base property, using %d.\n", ret); - return -EINVAL; - } + ud->match_data = (void *)dev_get_driver_data(dev); + ud->psil_base = ud->match_data->psil_base; ret = uclass_get_device_by_phandle(UCLASS_FIRMWARE, dev, "ti,sci", &tisci_dev); @@ -1723,8 +1736,7 @@ static int udma_of_xlate(struct dma *dma, struct ofnode_phandle_args *args) { struct udma_dev *ud = dev_get_priv(dma->dev); struct udma_chan *uc = &ud->channels[0]; - ofnode chconf_node, slave_node; - char prop[50]; + struct psil_endpoint_config *ep_config; u32 val; for (val = 0; val < ud->ch_count; val++) { @@ -1736,42 +1748,26 @@ static int udma_of_xlate(struct dma *dma, struct ofnode_phandle_args *args) if (val == ud->ch_count) return -EBUSY; - uc->dir = DMA_DEV_TO_MEM; - if (args->args[2] == UDMA_DIR_TX) + uc->slave_thread_id = args->args[0]; + if (uc->slave_thread_id & K3_PSIL_DST_THREAD_ID_OFFSET) uc->dir = DMA_MEM_TO_DEV; + else + uc->dir = DMA_DEV_TO_MEM; - slave_node = ofnode_get_by_phandle(args->args[0]); - if (!ofnode_valid(slave_node)) { - dev_err(ud->dev, "slave node is missing\n"); - return -EINVAL; - } - - snprintf(prop, sizeof(prop), "ti,psil-config%u", args->args[1]); - chconf_node = ofnode_find_subnode(slave_node, prop); - if (!ofnode_valid(chconf_node)) { - dev_err(ud->dev, "Channel configuration node is missing\n"); - return -EINVAL; - } - - if (!ofnode_read_u32(chconf_node, "linux,udma-mode", &val)) { - if (val == UDMA_PKT_MODE) - uc->pkt_mode = true; + ep_config = psil_get_ep_config(uc->slave_thread_id); + if (IS_ERR(ep_config)) { + dev_err(ud->dev, "No configuration for psi-l thread 0x%04x\n", + uc->slave_thread_id); + uc->dir = DMA_MEM_TO_MEM; + uc->slave_thread_id = -1; + return false; } - if (!ofnode_read_u32(chconf_node, "statictr-type", &val)) - uc->static_tr_type = val; + uc->pkt_mode = ep_config->pkt_mode; - uc->needs_epib = ofnode_read_bool(chconf_node, "ti,needs-epib"); - if (!ofnode_read_u32(chconf_node, "ti,psd-size", &val)) - uc->psd_size = val; - uc->metadata_size = (uc->needs_epib ? 16 : 0) + uc->psd_size; - - if (ofnode_read_u32(slave_node, "ti,psil-base", &val)) { - dev_err(ud->dev, "ti,psil-base is missing\n"); - return -EINVAL; - } - - uc->slave_thread_id = val + args->args[1]; + uc->needs_epib = ep_config->needs_epib; + uc->psd_size = ep_config->psd_size; + uc->metadata_size = (uc->needs_epib ? CPPI5_INFO0_HDESC_EPIB_SIZE : 0) + uc->psd_size; dma->id = uc->id; pr_debug("Allocated dma chn:%lu epib:%d psdata:%u meta:%u thread_id:%x\n", @@ -1859,10 +1855,73 @@ static const struct dma_ops udma_ops = { .get_cfg = udma_get_cfg, }; +static struct udma_match_data am654_main_data = { + .psil_base = 0x1000, + .enable_memcpy_support = true, + .statictr_z_mask = GENMASK(11, 0), + .rchan_oes_offset = 0x200, + .tpl_levels = 2, + .level_start_idx = { + [0] = 8, /* Normal channels */ + [1] = 0, /* High Throughput channels */ + }, +}; + +static struct udma_match_data am654_mcu_data = { + .psil_base = 0x6000, + .enable_memcpy_support = true, + .statictr_z_mask = GENMASK(11, 0), + .rchan_oes_offset = 0x200, + .tpl_levels = 2, + .level_start_idx = { + [0] = 2, /* Normal channels */ + [1] = 0, /* High Throughput channels */ + }, +}; + +static struct udma_match_data j721e_main_data = { + .psil_base = 0x1000, + .enable_memcpy_support = true, + .flags = UDMA_FLAG_PDMA_ACC32 | UDMA_FLAG_PDMA_BURST | UDMA_FLAG_TDTYPE, + .statictr_z_mask = GENMASK(23, 0), + .rchan_oes_offset = 0x400, + .tpl_levels = 3, + .level_start_idx = { + [0] = 16, /* Normal channels */ + [1] = 4, /* High Throughput channels */ + [2] = 0, /* Ultra High Throughput channels */ + }, +}; + +static struct udma_match_data j721e_mcu_data = { + .psil_base = 0x6000, + .enable_memcpy_support = true, + .flags = UDMA_FLAG_PDMA_ACC32 | UDMA_FLAG_PDMA_BURST | UDMA_FLAG_TDTYPE, + .statictr_z_mask = GENMASK(23, 0), + .rchan_oes_offset = 0x400, + .tpl_levels = 2, + .level_start_idx = { + [0] = 2, /* Normal channels */ + [1] = 0, /* High Throughput channels */ + }, +}; + static const struct udevice_id udma_ids[] = { - { .compatible = "ti,k3-navss-udmap" }, - { .compatible = "ti,j721e-navss-mcu-udmap" }, - { } + { + .compatible = "ti,am654-navss-main-udmap", + .data = (ulong)&am654_main_data, + }, + { + .compatible = "ti,am654-navss-mcu-udmap", + .data = (ulong)&am654_mcu_data, + }, { + .compatible = "ti,j721e-navss-main-udmap", + .data = (ulong)&j721e_main_data, + }, { + .compatible = "ti,j721e-navss-mcu-udmap", + .data = (ulong)&j721e_mcu_data, + }, + { /* Sentinel */ }, }; U_BOOT_DRIVER(ti_edma3) = {