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Sun, 17 May 2020 01:20:51 -0700 (PDT) Received: from rayagonda.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id b65sm11735427wmc.30.2020.05.17.01.20.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 May 2020 01:20:50 -0700 (PDT) From: Rayagonda Kokatanur To: u-boot@lists.denx.de, Simon Glass , Bharat Gooty Cc: Srinath Mannam , Rayagonda Kokatanur Subject: [PATCH v1 10/15] arm: dts: ns3: add PAXB PCIe host and phy node Date: Sun, 17 May 2020 13:49:40 +0530 Message-Id: <20200517081945.21282-11-rayagonda.kokatanur@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200517081945.21282-1-rayagonda.kokatanur@broadcom.com> References: <20200517081945.21282-1-rayagonda.kokatanur@broadcom.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean From: Srinath Mannam Add PAXB PCIe host controller and phy node for NS3. Signed-off-by: Srinath Mannam Signed-off-by: Rayagonda Kokatanur Reviewed-by: Simon Glass --- arch/arm/dts/ns3-board.dts | 36 +++++++++ arch/arm/dts/ns3.dtsi | 158 +++++++++++++++++++++++++++++++++++++ 2 files changed, 194 insertions(+) diff --git a/arch/arm/dts/ns3-board.dts b/arch/arm/dts/ns3-board.dts index f8e501c225..460ed39132 100644 --- a/arch/arm/dts/ns3-board.dts +++ b/arch/arm/dts/ns3-board.dts @@ -67,3 +67,39 @@ &sdio0 { status = "okay"; }; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&pcie2 { + status = "okay"; +}; + +&pcie3 { + status = "okay"; +}; + +&pcie4 { + status = "okay"; +}; + +&pcie5 { + status = "okay"; +}; + +&pcie6 { + status = "okay"; +}; + +&pcie7 { + status = "okay"; +}; + +&pcie8 { + status = "okay"; +}; diff --git a/arch/arm/dts/ns3.dtsi b/arch/arm/dts/ns3.dtsi index adb1277471..9fd59a855e 100644 --- a/arch/arm/dts/ns3.dtsi +++ b/arch/arm/dts/ns3.dtsi @@ -5,6 +5,11 @@ #include "skeleton64.dtsi" +#define PCIE_DMA_RANGES dma-ranges = < \ + 0x43000000 0x00 0x80000000 0x00 0x80000000 0x00 0x80000000 \ + 0x43000000 0x08 0x00000000 0x08 0x00000000 0x08 0x00000000 \ + 0x43000000 0x80 0x00000000 0x80 0x00000000 0x80 0x00000000> + / { compatible = "brcm,ns3"; #address-cells = <2>; @@ -89,4 +94,157 @@ <&pinmux 145 149 6>; }; }; + + pcie0: pcie@48000000 { + compatible = "brcm,iproc-pcie-paxb-v2"; + reg = <0 0x48000000 0 0x4000>; + bus-range = <0x0 0xff>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x83000000 0x0 0x42000000 0x0 0x42000000 0 0x2000000>, + <0x43000000 0x4 0x00000000 0x4 0x00000000 0 0x80000000>; + brcm,pcie-ob; + PCIE_DMA_RANGES; + phys = <&pcie_phy 0>; + phy-names = "pcie-phy"; + status = "disabled"; + }; + + pcie1: pcie@48004000 { + compatible = "brcm,iproc-pcie-paxb-v2"; + reg = <0 0x48004000 0 0x4000>; + bus-range = <0x0 0xff>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x83000000 0x0 0x44000000 0x0 0x44000000 0 0x2000000>, + <0x43000000 0x4 0x80000000 0x4 0x80000000 0 0x80000000>; + brcm,pcie-ob; + PCIE_DMA_RANGES; + phys = <&pcie_phy 1>; + phy-names = "pcie-phy"; + status = "disabled"; + }; + + pcie2: pcie@48008000 { + compatible = "brcm,iproc-pcie-paxb-v2"; + reg = <0 0x48008000 0 0x4000>; + bus-range = <0x0 0xff>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x83000000 0x0 0x4a000000 0x0 0x4a000000 0 0x2000000>, + <0x43000000 0x5 0x00000000 0x5 0x00000000 0 0x80000000>; + brcm,pcie-ob; + PCIE_DMA_RANGES; + phys = <&pcie_phy 2>; + phy-names = "pcie-phy"; + status = "disabled"; + }; + + pcie3: pcie@4800c000 { + compatible = "brcm,iproc-pcie-paxb-v2"; + reg = <0 0x4800c000 0 0x4000>; + bus-range = <0x0 0xff>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + brcm,pcie-ob; + ranges = <0x83000000 0x0 0x4c000000 0x0 0x4c000000 0 0x2000000>, + <0x43000000 0x5 0x80000000 0x5 0x80000000 0 0x80000000>; + PCIE_DMA_RANGES; + phys = <&pcie_phy 3>; + phy-names = "pcie-phy"; + status = "disabled"; + }; + + pcie4: pcie@48010000 { + compatible = "brcm,iproc-pcie-paxb-v2"; + reg = <0 0x48010000 0 0x4000>; + bus-range = <0x0 0xff>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + brcm,pcie-ob; + ranges = <0x83000000 0x0 0x52000000 0x0 0x52000000 0 0x2000000>, + <0x43000000 0x6 0x00000000 0x6 0x00000000 0 0x80000000>; + PCIE_DMA_RANGES; + phys = <&pcie_phy 4>; + phy-names = "pcie-phy"; + status = "disabled"; + }; + + pcie5: pcie@48014000 { + compatible = "brcm,iproc-pcie-paxb-v2"; + reg = <0 0x48014000 0 0x4000>; + bus-range = <0x0 0xff>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + brcm,pcie-ob; + ranges = <0x83000000 0x0 0x54000000 0x0 0x54000000 0 0x2000000>, + <0x43000000 0x6 0x80000000 0x6 0x80000000 0 0x80000000>; + PCIE_DMA_RANGES; + phys = <&pcie_phy 5>; + phy-names = "pcie-phy"; + status = "disabled"; + }; + + pcie6: pcie@48018000 { + compatible = "brcm,iproc-pcie-paxb-v2"; + reg = <0 0x48018000 0 0x4000>; + bus-range = <0x0 0xff>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + brcm,pcie-ob; + ranges = <0x83000000 0x0 0x5a000000 0x0 0x5a000000 0 0x2000000>, + <0x43000000 0x7 0x00000000 0x7 0x00000000 0 0x80000000>; + PCIE_DMA_RANGES; + phys = <&pcie_phy 6>; + phy-names = "pcie-phy"; + status = "disabled"; + }; + + pcie7: pcie@4801c000 { + compatible = "brcm,iproc-pcie-paxb-v2"; + reg = <0 0x4801c000 0 0x4000>; + bus-range = <0x0 0xff>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + brcm,pcie-ob; + ranges = <0x83000000 0x0 0x5c000000 0x0 0x5c000000 0 0x2000000>, + <0x43000000 0x8 0x00000000 0x8 0x00000000 0 0x80000000>; + PCIE_DMA_RANGES; + phys = <&pcie_phy 7>; + phy-names = "pcie-phy"; + status = "disabled"; + }; + + pcie8: pcie@60400000 { + compatible = "brcm,iproc-pcie-paxc-v2"; + reg = <0 0x60400000 0 0x1000>; + bus-range = <0x0 0x1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x83000000 0 0x10000000 0 0x10000000 0 0x20000000>; + status = "disabled"; + pci@0,0 { + compatible = "pci-bridge"; + reg = <0x0000 0 0 0 0>; + }; + }; + + pcie_phy: phy@0 { + compatible = "brcm,sr-pcie-phy"; + reg = <0 0x40000000 0 0x200>, + <0 0x6641d000 0 0x100>; + reg-names = "reg_base", "cdru_base"; + #address-cells = <3>; + #size-cells = <2>; + #phy-cells = <1>; + }; };