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Mon, 4 May 2020 12:45:45 +0000 (GMT) From: Sylwester Nawrocki To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com Cc: nsaenzjulienne@suse.de, sjg@chromium.org, jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com, Sylwester Nawrocki Subject: [PATCH v2 06/10] rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 32bit) Date: Mon, 4 May 2020 14:45:19 +0200 Message-Id: <20200504124523.23484-7-s.nawrocki@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200504124523.23484-1-s.nawrocki@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprEKsWRmVeSWpSXmKPExsWy7djP87qVfBviDA4+sLbYOGM9q8XUnniL G7/aWC3WHrnLbvGmrZHRYsHkJ6wW22YtZ7M4/Kad1eLblm2MFm/3drI7cHnMbrjI4jFv1gkW j52z7rJ7nL2zg9Gjb8sqRo/1W66yeGw+XR3AHsVlk5Kak1mWWqRvl8CVceDtDJaCSVIVZ7/5 NDBeE+1i5OSQEDCReNv0jLGLkYtDSGAFo8ShOZvZIJwvjBKtV3+wglQJCXxmlLjxJh2mY9Xp 01BFyxklll2bzgzX8X7mN0aQKjYBQ4neo31gtohAgMS1n9PAdjALrGSU+HDvGztIQlggXWLJ 9CVAKzg4WARUJfav0QQJ8wpYS3x93ssEsU1eYvWGA8wgNqeAjcSbpk8sIHMkBPrZJY53vYAq cpH4/OY4K4QtLPHq+BZ2CFtG4v/O+UwQDc2MEj27b7NDOBMYJe4fX8AIUWUtcefcLzaQK5gF NCXW79KHCDtKbFl9lB0kLCHAJ3HjrSBImBnInLQN5GOQMK9ER5sQRLWKxO9V06HOkZLofvKf BaLEQ2LucQdI+PQzSmxYO4tlAqP8LIRdCxgZVzGKp5YW56anFhvlpZbrFSfmFpfmpesl5+du YgSmlNP/jn/ZwbjrT9IhRgEORiUe3ojP6+OEWBPLiitzDzFKcDArifDuaAEK8aYkVlalFuXH F5XmpBYfYpTmYFES5zVe9DJWSCA9sSQ1OzW1ILUIJsvEwSnVwFj/NuFaeIfV5i8V73VT9sj/ OZXzkSnH5ISk/HKzG5lzNZ0TCzl/Xart6hFYEnZp7eZ10Y2xuj9WKosfnBrb/Wdb9bzZffl+ qS7ie9PSuj4zuwgUL+i/yi5vv3mn9PQf7KFxs3kWKj56uqRDUK+p4rzUx+hLHJtMGDR3FR8/ lXt2Y1ZlZoLoISWW4oxEQy3mouJEAEY0vEwlAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrILMWRmVeSWpSXmKPExsVy+t/xe7qVfBviDJZ1yltsnLGe1WJqT7zF jV9trBZrj9xlt3jT1shosWDyE1aLbbOWs1kcftPOavFtyzZGi7d7O9kduDxmN1xk8Zg36wSL x85Zd9k9zt7ZwejRt2UVo8f6LVdZPDafrg5gj9KzKcovLUlVyMgvLrFVija0MNIztLTQMzKx 1DM0No+1MjJV0rezSUnNySxLLdK3S9DLOPB2BkvBJKmKs998GhiviXYxcnJICJhIrDp9mg3E FhJYyigxodevi5EDKC4lMb9FCaJEWOLPtS6okk+MEo0T+UFsNgFDid6jfYwgtohAiMSLo1eY uhi5OJgF1jNKXDw/nxkkISyQKrHp7B5GkJksAqoS+9dogoR5Bawlvj7vZYKYLy+xesMBsHJO ARuJN02fWCB2WUvs/XGMbQIj3wJGhlWMIqmlxbnpucWGesWJucWleel6yfm5mxiBwb3t2M/N OxgvbQw+xCjAwajEwxvxeX2cEGtiWXFl7iFGCQ5mJRHeHS1AId6UxMqq1KL8+KLSnNTiQ4ym QDdNZJYSTc4HRl5eSbyhqaG5haWhubG5sZmFkjhvh8DBGCGB9MSS1OzU1ILUIpg+Jg5OqQbG CV2ir2acnsu93fvfSf3H7ucv2318Zvaz7nCmfHJzerlXVGtZi+PmjcF2n8U2iHw68uzEbDeH 3ZzHVH+4vdqw/f2H3mNBOy+4vpb71TK7eO3SC6XWsvXX/3EwrLscvvtx8alZWZOPBHt+c5np MtnL8LxuydbWHn5vISl3jY1Hpj55bO1w6jPHISWW4oxEQy3mouJEAB1F9U+EAgAA X-CMS-MailID: 20200504124545eucas1p2d8fcb6cfbd2204d171dad747cb6f9cd1 X-Msg-Generator: CA X-RootMTR: 20200504124545eucas1p2d8fcb6cfbd2204d171dad747cb6f9cd1 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20200504124545eucas1p2d8fcb6cfbd2204d171dad747cb6f9cd1 References: <20200504124523.23484-1-s.nawrocki@samsung.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean From: Marek Szyprowski Create a non-cacheable mapping for the 0x600000000 physical memory region, where MMIO registers for the PCIe XHCI controller are instantiated by the PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM 32bit mode, this region is mapped at 0xff800000 CPU virtual address. Signed-off-by: Marek Szyprowski Signed-off-by: Sylwester Nawrocki --- Changes since v1: - none. --- arch/arm/mach-bcm283x/Kconfig | 1 + arch/arm/mach-bcm283x/include/mach/base.h | 7 +++++ arch/arm/mach-bcm283x/init.c | 52 +++++++++++++++++++++++++++++++ 3 files changed, 60 insertions(+) diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig index 00419bf..bcb7f1d 100644 --- a/arch/arm/mach-bcm283x/Kconfig +++ b/arch/arm/mach-bcm283x/Kconfig @@ -36,6 +36,7 @@ config BCM2711_32B select BCM2711 select ARMV7_LPAE select CPU_V7A + select PHYS_64BIT config BCM2711_64B bool "Broadcom BCM2711 SoC 64-bit support" diff --git a/arch/arm/mach-bcm283x/include/mach/base.h b/arch/arm/mach-bcm283x/include/mach/base.h index c4ae398..1d10dc9 100644 --- a/arch/arm/mach-bcm283x/include/mach/base.h +++ b/arch/arm/mach-bcm283x/include/mach/base.h @@ -6,6 +6,13 @@ #ifndef _BCM283x_BASE_H_ #define _BCM283x_BASE_H_ +#include + extern unsigned long rpi_bcm283x_base; +#ifdef CONFIG_ARMV7_LPAE +extern void *rpi4_phys_to_virt(phys_addr_t paddr); +#define phys_to_virt(x) rpi4_phys_to_virt(x) +#endif + #endif diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c index 6a748da..5d0d160 100644 --- a/arch/arm/mach-bcm283x/init.c +++ b/arch/arm/mach-bcm283x/init.c @@ -145,6 +145,58 @@ int mach_cpu_init(void) } #ifdef CONFIG_ARMV7_LPAE + +#define BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT 0xff800000UL + +void *rpi4_phys_to_virt(phys_addr_t paddr) +{ + if (paddr >= BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS) + paddr = paddr - BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS + + BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT; + return (void *)(unsigned long)paddr; +} + +static void set_section_phys(unsigned int section, phys_addr_t phys, + enum dcache_option option) +{ + u64 *page_table = (u64 *)gd->arch.tlb_addr; + /* Need to set the access flag to not fault */ + u64 value = TTB_SECT_AP | TTB_SECT_AF; + + /* Add the page offset */ + value |= (phys); + + /* Add caching bits */ + value |= option; + + /* Set PTE */ + page_table[section] = value; +} + +static void rpi4_create_pcie_xhci_mapping(void) +{ + unsigned sect = BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT >> MMU_SECTION_SHIFT; + phys_addr_t phys_addr = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS; + unsigned int size = BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE; + + while (size) { + set_section_phys(sect, phys_addr, DCACHE_OFF); + sect++; + phys_addr += MMU_SECTION_SIZE; + size -= MMU_SECTION_SIZE; + } +} + +void arm_init_domains(void) +{ + /* + * Hijack this function to prepare a mappings for the PCIe MMIO + * region for the XHCI controller on RPi4 board. + * This code is called before enabling the MMU in ARM 32bit mode. + */ + rpi4_create_pcie_xhci_mapping(); +} + void enable_caches(void) { dcache_enable();