From patchwork Mon May 4 12:45:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sylwester Nawrocki X-Patchwork-Id: 1282593 X-Patchwork-Delegate: matthias.bgg@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=samsung.com header.i=@samsung.com header.a=rsa-sha256 header.s=mail20170921 header.b=Ip4YfWDh; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 49G2f664j2z9sSm for ; Mon, 4 May 2020 22:46:06 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 9902681F91; Mon, 4 May 2020 14:45:57 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=samsung.com header.i=@samsung.com header.b="Ip4YfWDh"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 6F6BB81FC4; Mon, 4 May 2020 14:45:55 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id A38FF81F9E for ; Mon, 4 May 2020 14:45:45 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=s.nawrocki@samsung.com Received: from eucas1p2.samsung.com (unknown [182.198.249.207]) by mailout1.w1.samsung.com (KnoxPortal) with ESMTP id 20200504124544euoutp01b53390b00bcd62429a16d1f7c5b30f44~L0-Vq9jFZ2175121751euoutp011 for ; Mon, 4 May 2020 12:45:44 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout1.w1.samsung.com 20200504124544euoutp01b53390b00bcd62429a16d1f7c5b30f44~L0-Vq9jFZ2175121751euoutp011 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1588596344; bh=o2n59jAOXed94iksPXrzyyjRiAB6FlEj8rUQ47ogyyk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ip4YfWDhzr1YHMHx6ORkw1+cn69/g3YOK9w7RwGn/p5MJbO03/LHYcTzTr7KUan7f Ky91yVXAztNOSgh/ILsF+jKCWM6AE3co7GX3nLgR6f57Jj5pexf3/LKJz+uDrblizh Bq7g1Mo6Tn0ZsvoanUBysmOAkkwgb9Xno4Y2fLoA= Received: from eusmges2new.samsung.com (unknown [203.254.199.244]) by eucas1p2.samsung.com (KnoxPortal) with ESMTP id 20200504124544eucas1p27a6f5e7634b4fbbdea858d46637bd551~L0-VgVuuY1023510235eucas1p28; Mon, 4 May 2020 12:45:44 +0000 (GMT) Received: from eucas1p1.samsung.com ( [182.198.249.206]) by eusmges2new.samsung.com (EUCPMTA) with SMTP id B5.A1.60679.87E00BE5; Mon, 4 May 2020 13:45:44 +0100 (BST) Received: from eusmtrp1.samsung.com (unknown [182.198.249.138]) by eucas1p1.samsung.com (KnoxPortal) with ESMTPA id 20200504124544eucas1p1dff0bc65bd0cdab0de2662c2671d49b3~L0-VLi5vn2649326493eucas1p1Y; Mon, 4 May 2020 12:45:44 +0000 (GMT) Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by eusmtrp1.samsung.com (KnoxPortal) with ESMTP id 20200504124544eusmtrp11e8ed3c00bf27338d90dc2b116f829a0~L0-VKmyrF1936819368eusmtrp15; Mon, 4 May 2020 12:45:44 +0000 (GMT) X-AuditID: cbfec7f4-0cbff7000001ed07-68-5eb00e78adc4 Received: from eusmtip2.samsung.com ( [203.254.199.222]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id 72.E4.07950.77E00BE5; Mon, 4 May 2020 13:45:44 +0100 (BST) Received: from AMDC3061.digital.local (unknown [106.120.51.75]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20200504124543eusmtip27af0f8cccf963424f55b2733c16ac0db~L0-Uu4ZsC2672526725eusmtip2Y; Mon, 4 May 2020 12:45:43 +0000 (GMT) From: Sylwester Nawrocki To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com Cc: nsaenzjulienne@suse.de, sjg@chromium.org, jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com, Sylwester Nawrocki Subject: [PATCH v2 03/10] pci: Move some PCIe register offset definitions to a common header Date: Mon, 4 May 2020 14:45:16 +0200 Message-Id: <20200504124523.23484-4-s.nawrocki@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200504124523.23484-1-s.nawrocki@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSXUhTYRzGez1nO2ej2Wku/GeROI1KaGZFHFCiwot550WBJH5MPai0zbGj 84vANKyW+TVtalImhkutuVybWWGuTGlqZRaGWheakGxQaQM/0jaP1t3v/zz/5314X14SExt4 QWSWOofRqhVKKV+I214vjR7O9+9KOjJwQ0Jb6s08uq48mZ5YLuPRD15NE7Sr7BKimw2zPNrW 2ManX7qu8GiP1YZo9/NrxCmh/Fbxe1x+u3EIlz9pnCbkI1M9SF5hbUdys/UjLu92FsUR54XR 6YwyS8doI06mCDMNTSEa4+78mbvrqBjNSfRIQAJ1HKanWnk+FlMmBD/6zuiR0MuLCPqr+/jc sICg6bcFbSUs9j84Z7QhaLF70L/IuGNu4yw+FQk3Bio2EhIqDj4t3dxYwqj73o4vHsJnBFBJ MDw54edjnNoP6xNuTI9IUkRFQd/ndK4tGDq6XmA+FlDR4Cr5tdEMlIGAqp8fCG4pBtytTozj AJgftG7qe8FpKN8MlCIofzpJcEMVgq+DzZsXioKp0WW+rxmjDoG5N4KTT8PanVLCJwPlDxPu nT4Z82KNzYhxsgiulom57TBYaTf6cRwE12fXcY7l0F3/kMc9UCWCTv0MqkLBjf/LmhFqR4FM LqvKYNijaiZPxipUbK46Q5aWrXqEvF/FuTa42IN6V1MdiCKRdLsofsGcJOYpdGyByoGAxKQS Uc9lryRKVxQUMtrsZG2ukmEdaA+JSwNFx1q+J4qpDEUOc4FhNIx2y/UjBUHFKKHorTKv5OKY s7ywuP/xwmznaoJt27dRmgitTQRT+ErICUnSsiYhNN7KDxVEDmfJPA2uXfpxpfFZPr/u3YKJ VIWtmC12ie2eqbA7NuSAYyY1boxNTDHFqtMWGY9gR1xlx9nCfVntDUNT9phaSqMbqA5/c/Cc riZ4fKRBNi/F2UxFZDimZRV/AdJpF3MmAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrELMWRmVeSWpSXmKPExsVy+t/xe7oVfBviDN4fYrTYOGM9q8XUnniL G7/aWC3WHrnLbvGmrZHRYsHkJ6wW22YtZ7M4/Kad1eLblm2MFm/3drI7cHnMbrjI4jFv1gkW j52z7rJ7nL2zg9Gjb8sqRo/1W66yeGw+XR3AHqVnU5RfWpKqkJFfXGKrFG1oYaRnaGmhZ2Ri qWdobB5rZWSqpG9nk5Kak1mWWqRvl6CXMXmOYsF0yYrHC/8zNjA+E+li5OSQEDCR2Lj9L0sX IxeHkMBSRonl078DORxACSmJ+S1KEDXCEn+udbFB1HxilHg78wczSIJNwFCi92gfI4gtIhAi 8eLoFSaQImaB9YwSF8/PZwYZJCwQI3GzxwGkhkVAVeL/jbdgYV4Ba4n9N1Mg5stLrN5wAGwk p4CNxJumTywgthBQyd4fx9gmMPItYGRYxSiSWlqcm55bbKRXnJhbXJqXrpecn7uJERje2479 3LKDsetd8CFGAQ5GJR7eDV/XxwmxJpYVV+YeYpTgYFYS4d3RAhTiTUmsrEotyo8vKs1JLT7E aAp000RmKdHkfGDs5ZXEG5oamltYGpobmxubWSiJ83YIHIwREkhPLEnNTk0tSC2C6WPi4JRq YNSfyxdjq7P0oZTNxsxNRfNyV71/k34ydv2FB280Z6avTjbxXnte56TF+6OzdVOPfY5iit0S dk120Zp8+8biTeuM57H9O5PKdma7in/kjftnQiKOPrx/U/lY43VbtbjU9q6O2On6XyUZTNLe aCkePPTj9EW3x1O9gu6IqzaKHxF/sOlE82cPCQMlluKMREMt5qLiRACvvGZThQIAAA== X-CMS-MailID: 20200504124544eucas1p1dff0bc65bd0cdab0de2662c2671d49b3 X-Msg-Generator: CA X-RootMTR: 20200504124544eucas1p1dff0bc65bd0cdab0de2662c2671d49b3 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20200504124544eucas1p1dff0bc65bd0cdab0de2662c2671d49b3 References: <20200504124523.23484-1-s.nawrocki@samsung.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki Reviewed-by: Bin Meng Reviewed-by: Nicolas Saenz Julienne --- Changes since v1: - none. Changes since RFC: - whitespace clean up. --- drivers/pci/pci-rcar-gen3.c | 8 -------- drivers/pci/pcie_intel_fpga.c | 3 --- include/pci.h | 13 +++++++++++-- 3 files changed, 11 insertions(+), 13 deletions(-) diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c index 30eff67..393f1c9 100644 --- a/drivers/pci/pci-rcar-gen3.c +++ b/drivers/pci/pci-rcar-gen3.c @@ -117,14 +117,6 @@ #define RCAR_PCI_MAX_RESOURCES 4 #define MAX_NR_INBOUND_MAPS 6 -#define PCI_EXP_FLAGS 2 /* Capabilities register */ -#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ -#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ -#define PCI_EXP_LNKCAP 12 /* Link Capabilities */ -#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ -#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ -#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ - enum { RCAR_PCI_ACCESS_READ, RCAR_PCI_ACCESS_WRITE, diff --git a/drivers/pci/pcie_intel_fpga.c b/drivers/pci/pcie_intel_fpga.c index 6a9f29c..69363a0 100644 --- a/drivers/pci/pcie_intel_fpga.c +++ b/drivers/pci/pcie_intel_fpga.c @@ -65,9 +65,6 @@ #define IS_ROOT_PORT(pcie, bdf) \ ((PCI_BUS(bdf) == pcie->first_busno) ? true : false) -#define PCI_EXP_LNKSTA 18 /* Link Status */ -#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ - /** * struct intel_fpga_pcie - Intel FPGA PCIe controller state * @bus: Pointer to the PCI bus diff --git a/include/pci.h b/include/pci.h index aff56b2..dfdbb32 100644 --- a/include/pci.h +++ b/include/pci.h @@ -471,10 +471,19 @@ #define PCI_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */ /* PCI Express capabilities */ +#define PCI_EXP_FLAGS 2 /* Capabilities register */ +#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ +#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ #define PCI_EXP_DEVCAP 4 /* Device capabilities */ -#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ +#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ #define PCI_EXP_DEVCTL 8 /* Device Control */ -#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ +#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ +#define PCI_EXP_LNKCAP 12 /* Link Capabilities */ +#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ +#define PCI_EXP_LNKSTA 18 /* Link Status */ +#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ +#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ +#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ /* Include the ID list */