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Fri, 24 Apr 2020 16:52:07 +0000 (GMT) From: Sylwester Nawrocki To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com Cc: sjg@chromium.org, nsaenzjulienne@suse.de, jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com Subject: [PATCH v1 06/10] rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 32bit) Date: Fri, 24 Apr 2020 18:50:08 +0200 Message-Id: <20200424165012.31915-7-s.nawrocki@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200424165012.31915-1-s.nawrocki@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupileLIzCtJLcpLzFFi42LZduzneV1LycVxBuumcllsnLGe1WJqT7zF jV9trBZrj9xlt3jT1shosWDyE1aLbbOWs1l827KN0eLt3k52B06P2Q0XWTzmzTrB4rFz1l12 j7N3djB69G1ZxeixfstVFo/Np6sD2KO4bFJSczLLUov07RK4Mq4sUiu4Llnx6fRe5gbGBaJd jBwcEgImEt8WRHYxcnEICaxglFgw5wwLhPOFUeL+5g/sXYycQM5nRonerdogNkjDsY17mSGK ljNK7Dq4mhWuY+H0zawgVWwChhK9R/sYQWwRgQCJaz+ngdnMAlUS19ufsoDYwgLpEq1Hl4LF WQRUJRZsfwhm8wpYS/xtOsQKsU1eYvWGA8wgNqeAjUTj2Vdg50kIdLNL/D/QxQbxg4vEvSXh EPXCEq+Ob2GHsGUkTk/ugapvZpTo2X2bHcKZAPTb8QWMEFXWEnfO/QIbxCygKbF+lz7ETEeJ b8d0IEw+iRtvBSHO55OYtG06M0SYV6KjTQhihorE71XTmSBsKYnuJ/9ZIEo8JDa3x0FCp59R Ys7S6UwTGOVnIaxawMi4ilE8tbQ4Nz212DgvtVyvODG3uDQvXS85P3cTIzCFnP53/OsOxn1/ kg4xCnAwKvHwRhxZFCfEmlhWXJl7iFGCg1lJhDemBCjEm5JYWZValB9fVJqTWnyIUZqDRUmc 13jRy1ghgfTEktTs1NSC1CKYLBMHp1QD46aLfYeY7TyTnrmzFOn8s4t64nBh7XefvK7SzrC9 d+48OOcetXbG1knm0z+su1K4cEYFk0uowKujWaaTjl2bbLdgilHUyd+LZ08KXXQouHvl5vif Dbc3qV964OOWIsslW6s1XebHmiCrD0/MPmntnZ2295FSVE1cn8+bp3euHi/RvP+jtaLwb6gS S3FGoqEWc1FxIgAUAtMEHQMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrPLMWRmVeSWpSXmKPExsVy+t/xe7oWkovjDHq2yFhsnLGe1WJqT7zF jV9trBZrj9xlt3jT1shosWDyE1aLbbOWs1l827KN0eLt3k52B06P2Q0XWTzmzTrB4rFz1l12 j7N3djB69G1ZxeixfstVFo/Np6sD2KP0bIryS0tSFTLyi0tslaINLYz0DC0t9IxMLPUMjc1j rYxMlfTtbFJSczLLUov07RL0Mq4sUiu4Llnx6fRe5gbGBaJdjJwcEgImEsc27mXuYuTiEBJY yihxZUoLaxcjB1BCSmJ+ixJEjbDEn2tdbBA1nxgl1m38zwSSYBMwlOg92scIYosIhEi8OHqF CaSIWaCBUeLe0TmsIAlhgVSJexM+ghWxCKhKLNj+EMzmFbCW+Nt0iBVig7zE6g0HmEFsTgEb icazr1hAbCGgmm0zn7NMYORbwMiwilEktbQ4Nz232FCvODG3uDQvXS85P3cTIzCwtx37uXkH 46WNwYcYBTgYlXh4I44sihNiTSwrrsw9xCjBwawkwhtTAhTiTUmsrEotyo8vKs1JLT7EaAp0 1ERmKdHkfGDU5ZXEG5oamltYGpobmxubWSiJ83YIHIwREkhPLEnNTk0tSC2C6WPi4JRqYJx8 eZcGv/D8Xy/v1uZJqczekrFe6WYJy3OVpeHBq9+LHfTdNovPqEqSvdsnuLe29eJshblS9zk3 HK+zamyUcKzLE9q1InOt34eGJ/NlKyf+Wxy72kurmm9jiU9sneOxkk2dS7a3b147y9znCevt V6dPZxy0W5T8ymdqLevUyLW5ReZdLfoFd5VYijMSDbWYi4oTAWa/WtmCAgAA X-CMS-MailID: 20200424165208eucas1p23af382ac8bdacf0bc94b2b0f027e4541 X-Msg-Generator: CA X-RootMTR: 20200424165208eucas1p23af382ac8bdacf0bc94b2b0f027e4541 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20200424165208eucas1p23af382ac8bdacf0bc94b2b0f027e4541 References: <20200424165012.31915-1-s.nawrocki@samsung.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean From: Marek Szyprowski Create a non-cacheable mapping for the 0x600000000 physical memory region, where MMIO registers for the PCIe XHCI controller are instantiated by the PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM 32bit mode, this region is mapped at 0xff800000 CPU virtual address. Signed-off-by: Marek Szyprowski --- Changes since RFC: - none. --- arch/arm/mach-bcm283x/Kconfig | 1 + arch/arm/mach-bcm283x/include/mach/base.h | 7 +++++ arch/arm/mach-bcm283x/init.c | 52 +++++++++++++++++++++++++++++++ 3 files changed, 60 insertions(+) diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig index 00419bf..bcb7f1d 100644 --- a/arch/arm/mach-bcm283x/Kconfig +++ b/arch/arm/mach-bcm283x/Kconfig @@ -36,6 +36,7 @@ config BCM2711_32B select BCM2711 select ARMV7_LPAE select CPU_V7A + select PHYS_64BIT config BCM2711_64B bool "Broadcom BCM2711 SoC 64-bit support" diff --git a/arch/arm/mach-bcm283x/include/mach/base.h b/arch/arm/mach-bcm283x/include/mach/base.h index c4ae398..1d10dc9 100644 --- a/arch/arm/mach-bcm283x/include/mach/base.h +++ b/arch/arm/mach-bcm283x/include/mach/base.h @@ -6,6 +6,13 @@ #ifndef _BCM283x_BASE_H_ #define _BCM283x_BASE_H_ +#include + extern unsigned long rpi_bcm283x_base; +#ifdef CONFIG_ARMV7_LPAE +extern void *rpi4_phys_to_virt(phys_addr_t paddr); +#define phys_to_virt(x) rpi4_phys_to_virt(x) +#endif + #endif diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c index 6a748da..5d0d160 100644 --- a/arch/arm/mach-bcm283x/init.c +++ b/arch/arm/mach-bcm283x/init.c @@ -145,6 +145,58 @@ int mach_cpu_init(void) } #ifdef CONFIG_ARMV7_LPAE + +#define BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT 0xff800000UL + +void *rpi4_phys_to_virt(phys_addr_t paddr) +{ + if (paddr >= BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS) + paddr = paddr - BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS + + BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT; + return (void *)(unsigned long)paddr; +} + +static void set_section_phys(unsigned int section, phys_addr_t phys, + enum dcache_option option) +{ + u64 *page_table = (u64 *)gd->arch.tlb_addr; + /* Need to set the access flag to not fault */ + u64 value = TTB_SECT_AP | TTB_SECT_AF; + + /* Add the page offset */ + value |= (phys); + + /* Add caching bits */ + value |= option; + + /* Set PTE */ + page_table[section] = value; +} + +static void rpi4_create_pcie_xhci_mapping(void) +{ + unsigned sect = BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT >> MMU_SECTION_SHIFT; + phys_addr_t phys_addr = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS; + unsigned int size = BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE; + + while (size) { + set_section_phys(sect, phys_addr, DCACHE_OFF); + sect++; + phys_addr += MMU_SECTION_SIZE; + size -= MMU_SECTION_SIZE; + } +} + +void arm_init_domains(void) +{ + /* + * Hijack this function to prepare a mappings for the PCIe MMIO + * region for the XHCI controller on RPi4 board. + * This code is called before enabling the MMU in ARM 32bit mode. + */ + rpi4_create_pcie_xhci_mapping(); +} + void enable_caches(void) { dcache_enable();