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d="scan'208";a="135816953" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 22 Apr 2020 02:15:16 +0800 IronPort-SDR: LOHKBiw+Y8pwacfecRBjqmkuzIB/xzKCfS3EqRG3PVjDtYXGWvjHRBZRu3vXG9cExjQ2WD7aqL r9NRlO5ff4VoSSqfa0IBatGE7I9fdjycI= Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2020 11:05:34 -0700 IronPort-SDR: 6MbMH/2xNVyRE1FdIlDcRmTQbgIy91NvuYd7ih9XoDWA9T1WoYU/XwdEtRn1OH7q6xb/1kPkKW dQvHMKPorctA== WDCIronportException: Internal Received: from usa001638.ad.shared (HELO yoda.hgst.com) ([10.86.55.248]) by uls-op-cesaip01.wdc.com with ESMTP; 21 Apr 2020 11:15:17 -0700 From: Atish Patra To: u-boot@lists.denx.de Cc: Atish Patra , Bin Meng , Anup Patel , Lukas Auer , Heinrich Schuchardt , Rick Chen , palmer@dabbelt.com Subject: [PATCH v7 5/6] riscv: Copy the reserved-memory nodes to final DT Date: Tue, 21 Apr 2020 11:15:03 -0700 Message-Id: <20200421181504.415822-6-atish.patra@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200421181504.415822-1-atish.patra@wdc.com> References: <20200421181504.415822-1-atish.patra@wdc.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean The DT used by U-Boot may be different from the DT being passed to the OS if the DT is loaded from external media such as network or mmc. In that case, the reserved-memory node needs to be copied to the DT passed to the OS. Signed-off-by: Atish Patra Reviewed-by: Bin Meng Tested-by: Bin Meng --- arch/riscv/lib/bootm.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index 87cadad5016d..8ff8db6bf533 100644 --- a/arch/riscv/lib/bootm.c +++ b/arch/riscv/lib/bootm.c @@ -28,8 +28,8 @@ __weak void board_quiesce_devices(void) int arch_fixup_fdt(void *blob) { -#ifdef CONFIG_EFI_LOADER int err; +#ifdef CONFIG_EFI_LOADER u32 size; int chosen_offset; @@ -50,6 +50,12 @@ int arch_fixup_fdt(void *blob) /* Overwrite the boot-hartid as U-Boot is the last stage BL */ fdt_setprop_u32(blob, chosen_offset, "boot-hartid", gd->arch.boot_hart); #endif + + /* Copy the reserved-memory node to the DT used by OS */ + err = riscv_fdt_copy_resv_mem_node(gd->fdt_blob, blob); + if (err < 0) + return err; + return 0; }