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Tue, 21 Apr 2020 16:51:22 +0000 (GMT) From: Sylwester Nawrocki To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com Cc: agraf@suse.de, sjg@chrmium.org, jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com Subject: [RFC PATCH 5/9] rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 32bit) Date: Tue, 21 Apr 2020 18:50:55 +0200 Message-Id: <20200421165059.19394-6-s.nawrocki@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200421165059.19394-1-s.nawrocki@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFuplleLIzCtJLcpLzFFi42LZduzned1ulflxBi8vWlmcuPKP0WLjjPWs FlN74i1u/GpjtVh75C67xZu2RkaLBZOfsFp0XP3PaPF2bye7A6fH/VMNrB7zZp1g8dg56y67 x9k7Oxg9+rasYvRYv+Uqi8fm09UB7FFcNimpOZllqUX6dglcGefnzWMp2CJZsf/SSqYGxnbR LkZODgkBE4lTm2cxg9hCAisYJa6sUOpi5AKyvzBK7Pv6iQnC+cwoceHlCSCHA6zj0ndfiPhy RolDOw6xwXUseN7FBjKKTcBQovdoHyOILSIQIHHt5zQwm1mgQGLa9SdsIIOEBdIk1q2PBgmz CKhK/H/RD1bCK2At0TFxJxPEdfISqzccALuOU8BG4u73GSwguyQE2tklOv78Y4MocpHYMes8 M4QtLPHq+BZ2CFtG4v/O+UwQDc2MEj27b7NDOBMYJe4fX8AIUWUtcefcL7CLmAU0Jdbv0ocI O0r8m9nGAvExn8SNt4IQ9/NJTNo2nRkizCvR0SYEUa0i8XvVdKibpSS6n/xngbA9JG6dPA4N n35GiePvzjFNYJSfhbBsASPjKkbx1NLi3PTUYqO81HK94sTc4tK8dL3k/NxNjMBEcvrf8S87 GHf9STrEKMDBqMTDe+P8vDgh1sSy4srcQ4wSHMxKIrwbHgKFeFMSK6tSi/Lji0pzUosPMUpz sCiJ8xovehkrJJCeWJKanZpakFoEk2Xi4JRqYMycbb2Z6X6zsffx891uL9M/pBpM6e2R1eC9 abXvg86THVnXDczb86Y+OMHaoPR/br7E63VbvxR+W2dz0rk55FRyaoRhh0zfOdW+qE8RhULe uua2f/9Er3VKF+SdfO+WeUdN1OvHCeb8hSZMUmWns/kD5+YUcs2ruebh9cbjSfyOudeaOG+u UGIpzkg01GIuKk4EAPSLu8IgAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrHLMWRmVeSWpSXmKPExsVy+t/xu7rdKvPjDPZOELc4ceUfo8XGGetZ Lab2xFvc+NXGarH2yF12izdtjYwWCyY/YbXouPqf0eLt3k52B06P+6caWD3mzTrB4rFz1l12 j7N3djB69G1ZxeixfstVFo/Np6sD2KP0bIryS0tSFTLyi0tslaINLYz0DC0t9IxMLPUMjc1j rYxMlfTtbFJSczLLUov07RL0Ms7Pm8dSsEWyYv+llUwNjO2iXYwcHBICJhKXvvt2MXJxCAks ZZSYeGIiG0RcSmJ+i1IXIyeQKSzx51oXG0TNJ6CaT0tYQRJsAoYSvUf7GEFsEYEQiRdHrzCB 2MwCZRJrWl+DxYUFUiSuXF3EAmKzCKhK/H/RDxbnFbCW6Ji4kwligbzE6g0HmEFsTgEbibvf Z4DVCwHVNFxawjKBkW8BI8MqRpHU0uLc9NxiQ73ixNzi0rx0veT83E2MwLDeduzn5h2MlzYG H2IU4GBU4uG9cX5enBBrYllxZe4hRgkOZiUR3g0PgUK8KYmVValF+fFFpTmpxYcYTYGOmsgs JZqcD4y5vJJ4Q1NDcwtLQ3Njc2MzCyVx3g6BgzFCAumJJanZqakFqUUwfUwcnFINjBb7jphd cHW99k349Za3DneDPqszyswoTlnxNfKtkWFuc5Csol6xgNDNrf81Vl0WSrujb8a/c0dDBov1 VuvDybd359g1/47sUkpb+OjKVF6W8u93CmvurMn8qPdFbQ5v7o0PSkKqc6qO/5uycZf73oz0 /OnXBAqkdeRl7nGl6t3qNFCMTqgxV2Ipzkg01GIuKk4EAH1/U2eBAgAA X-CMS-MailID: 20200421165123eucas1p171701bd64ed84a9c740331ce87c7ff6c X-Msg-Generator: CA X-RootMTR: 20200421165123eucas1p171701bd64ed84a9c740331ce87c7ff6c X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20200421165123eucas1p171701bd64ed84a9c740331ce87c7ff6c References: <20200421165059.19394-1-s.nawrocki@samsung.com> X-Mailman-Approved-At: Tue, 21 Apr 2020 19:40:20 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean From: Marek Szyprowski Create a non-cacheable mapping for the 0x600000000 physical memory region, where MMIO registers for the PCIe XHCI controller are instantiated by the PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM 32bit mode, this region is mapped at 0xff800000 CPU virtual address. Signed-off-by: Marek Szyprowski --- arch/arm/mach-bcm283x/Kconfig | 1 + arch/arm/mach-bcm283x/include/mach/base.h | 7 +++++ arch/arm/mach-bcm283x/init.c | 52 +++++++++++++++++++++++++++++++ 3 files changed, 60 insertions(+) diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig index 00419bf..bcb7f1d 100644 --- a/arch/arm/mach-bcm283x/Kconfig +++ b/arch/arm/mach-bcm283x/Kconfig @@ -36,6 +36,7 @@ config BCM2711_32B select BCM2711 select ARMV7_LPAE select CPU_V7A + select PHYS_64BIT config BCM2711_64B bool "Broadcom BCM2711 SoC 64-bit support" diff --git a/arch/arm/mach-bcm283x/include/mach/base.h b/arch/arm/mach-bcm283x/include/mach/base.h index c4ae398..1d10dc9 100644 --- a/arch/arm/mach-bcm283x/include/mach/base.h +++ b/arch/arm/mach-bcm283x/include/mach/base.h @@ -6,6 +6,13 @@ #ifndef _BCM283x_BASE_H_ #define _BCM283x_BASE_H_ +#include + extern unsigned long rpi_bcm283x_base; +#ifdef CONFIG_ARMV7_LPAE +extern void *rpi4_phys_to_virt(phys_addr_t paddr); +#define phys_to_virt(x) rpi4_phys_to_virt(x) +#endif + #endif diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c index 6a748da..5d0d160 100644 --- a/arch/arm/mach-bcm283x/init.c +++ b/arch/arm/mach-bcm283x/init.c @@ -145,6 +145,58 @@ int mach_cpu_init(void) } #ifdef CONFIG_ARMV7_LPAE + +#define BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT 0xff800000UL + +void *rpi4_phys_to_virt(phys_addr_t paddr) +{ + if (paddr >= BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS) + paddr = paddr - BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS + + BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT; + return (void *)(unsigned long)paddr; +} + +static void set_section_phys(unsigned int section, phys_addr_t phys, + enum dcache_option option) +{ + u64 *page_table = (u64 *)gd->arch.tlb_addr; + /* Need to set the access flag to not fault */ + u64 value = TTB_SECT_AP | TTB_SECT_AF; + + /* Add the page offset */ + value |= (phys); + + /* Add caching bits */ + value |= option; + + /* Set PTE */ + page_table[section] = value; +} + +static void rpi4_create_pcie_xhci_mapping(void) +{ + unsigned sect = BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT >> MMU_SECTION_SHIFT; + phys_addr_t phys_addr = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS; + unsigned int size = BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE; + + while (size) { + set_section_phys(sect, phys_addr, DCACHE_OFF); + sect++; + phys_addr += MMU_SECTION_SIZE; + size -= MMU_SECTION_SIZE; + } +} + +void arm_init_domains(void) +{ + /* + * Hijack this function to prepare a mappings for the PCIe MMIO + * region for the XHCI controller on RPi4 board. + * This code is called before enabling the MMU in ARM 32bit mode. + */ + rpi4_create_pcie_xhci_mapping(); +} + void enable_caches(void) { dcache_enable();