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Mon, 06 Apr 2020 00:15:34 -0700 (PDT) Received: from rayagonda.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id g3sm10881235wrw.47.2020.04.06.00.15.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Apr 2020 00:15:33 -0700 (PDT) From: Rayagonda Kokatanur To: u-boot@lists.denx.de, Stefan Roese , Qiang Zhao , Thomas Schaefer , Simon Glass , Bharat Kumar Reddy Gooty , vladimir.olovyannikov@broadcom.com Cc: Rayagonda Kokatanur Subject: [PATCH v3 1/1] driver: watchdog: get platform clock from dt file Date: Mon, 6 Apr 2020 12:45:20 +0530 Message-Id: <20200406071520.27947-1-rayagonda.kokatanur@broadcom.com> X-Mailer: git-send-email 2.17.1 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean Get the watchdog platform clock from the DTS file using clk subsystem and use the same for calculating ticks in msec. Signed-off-by: Rayagonda Kokatanur Signed-off-by: Bharat Kumar Reddy Gooty --- Changes from v2: -Address review comments from Stefan Roese, Use clk subsystem to get the base frequency of device instead of dt parameter "clk_mhz". Changes from v1: -Address review comments from Stefan Roese, Remove default timeout reading in probe() as it is read in include/wdt.h. Add paranthesis on multi-line statements. drivers/watchdog/sp805_wdt.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/watchdog/sp805_wdt.c b/drivers/watchdog/sp805_wdt.c index ca3ccbe76c..d377ae0fc5 100644 --- a/drivers/watchdog/sp805_wdt.c +++ b/drivers/watchdog/sp805_wdt.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -34,6 +35,7 @@ DECLARE_GLOBAL_DATA_PTR; struct sp805_wdt_priv { void __iomem *reg; + unsigned long clk_rate; }; static int sp805_wdt_reset(struct udevice *dev) @@ -63,8 +65,13 @@ static int sp805_wdt_start(struct udevice *dev, u64 timeout, ulong flags) * set 120s, the gd->bus_clk is less than 1145MHz, the load_value will * not overflow. */ - load_value = (gd->bus_clk) / - (2 * 1000 * SYS_FSL_WDT_CLK_DIV) * load_time; + if (gd->bus_clk) { + load_value = (gd->bus_clk) / + (2 * 1000 * SYS_FSL_WDT_CLK_DIV) * load_time; + } else { + /* platform provide clk */ + load_value = (timeout / 2) * (priv->clk_rate / 1000); + } writel(UNLOCK, priv->reg + WDTLOCK); writel(load_value, priv->reg + WDTLOAD); @@ -105,11 +112,19 @@ static int sp805_wdt_probe(struct udevice *dev) static int sp805_wdt_ofdata_to_platdata(struct udevice *dev) { struct sp805_wdt_priv *priv = dev_get_priv(dev); + struct clk clk; + int ret; priv->reg = (void __iomem *)dev_read_addr(dev); if (IS_ERR(priv->reg)) return PTR_ERR(priv->reg); + ret = clk_get_by_index(dev, 0, &clk); + if (!ret) + priv->clk_rate = clk_get_rate(&clk); + else + return -EINVAL; + return 0; }