From patchwork Fri Feb 14 11:54:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 1238002 X-Patchwork-Delegate: yamada.m@jp.panasonic.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=socionext.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nifty.com header.i=@nifty.com header.a=rsa-sha256 header.s=dec2015msa header.b=Lro9SfIk; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48JsJy5P5Sz9s29 for ; Fri, 14 Feb 2020 22:55:46 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 8CAFA81285; Fri, 14 Feb 2020 12:55:37 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=socionext.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=nifty.com header.i=@nifty.com header.b="Lro9SfIk"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 8234F8127D; Fri, 14 Feb 2020 12:55:34 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,SPF_HELO_NONE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from conuserg-09.nifty.com (conuserg-09.nifty.com [210.131.2.76]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id B1E258123C for ; Fri, 14 Feb 2020 12:55:30 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=socionext.com Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=yamada.masahiro@socionext.com Received: from localhost.localdomain (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-09.nifty.com with ESMTP id 01EBsnN9025859; Fri, 14 Feb 2020 20:54:50 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com 01EBsnN9025859 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1581681290; bh=KWngFnFUni4kzFvdRW7pzQCiN7c5sffqH0VXFKg1Y84=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Lro9SfIkni4i9NwETPSPp/dn1K4/T5nw6NTM5VZPlMCv4MgmEz5sF4GRMeSjEoLhH d6wfKunc5AKkL95wEKqh6Fqum7SaW2QVCWTkXarkXBwkZp1qgoiUN3J6egKWZcF0Am z6jAZ1HEuDCBP5/23V4E03tFt2JC+ucvPNmQjG1FXl82nSf0lbXR7kzQCJVt4XUYNm OThbjo7mbOKBiWypj4iA6yvgVeA7shXlfbQoYS7uuZcA/WMQCzOfQrIyPqofn821cL giMNwPWTWrlYXH7WsRdVT7BaWKMGE9fTNBhXsHpz93zcs5CB7YVcglKCDOs4+LP760 sm9zuHKNLDSug== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Cc: Masahiro Yamada , Tom Rini Subject: [PATCH 2/3] ARM: uniphier: remove workaround for the NAND write protect Date: Fri, 14 Feb 2020 20:54:41 +0900 Message-Id: <20200214115442.7166-2-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200214115442.7166-1-yamada.masahiro@socionext.com> References: <20200214115442.7166-1-yamada.masahiro@socionext.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.1 at phobos.denx.de X-Virus-Status: Clean This workaround was previously needed for LD4, Pro4, sLD8, Pro5 SoCs. The boot ROM does not touch this register for PXs2/LD6b or later. Now that the reset signal of the Denali NAND controller is always asserted in board_init() then deasserted in the driver, the WRITE_PROTECT register gets back to the default value, which means the write protect is deasserted. This workaround can go away entirely. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/board_late_init.c | 17 ----------------- 1 file changed, 17 deletions(-) diff --git a/arch/arm/mach-uniphier/board_late_init.c b/arch/arm/mach-uniphier/board_late_init.c index 793283058c35..378aad0c9c45 100644 --- a/arch/arm/mach-uniphier/board_late_init.c +++ b/arch/arm/mach-uniphier/board_late_init.c @@ -14,25 +14,9 @@ #include #include #include -#include <../drivers/mtd/nand/raw/denali.h> #include "init.h" -static void nand_denali_wp_disable(void) -{ -#ifdef CONFIG_NAND_DENALI - /* - * Since the boot rom enables the write protection for NAND boot mode, - * it must be disabled somewhere for "nand write", "nand erase", etc. - * The workaround is here to not disturb the Denali NAND controller - * driver just for a really SoC-specific thing. - */ - void __iomem *denali_reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE; - - writel(WRITE_PROTECT__FLAG, denali_reg + WRITE_PROTECT); -#endif -} - static void uniphier_set_env_fdt_file(void) { DECLARE_GLOBAL_DATA_PTR; @@ -114,7 +98,6 @@ int board_late_init(void) case BOOT_DEVICE_NAND: printf("NAND Boot"); env_set("bootdev", "nand"); - nand_denali_wp_disable(); break; case BOOT_DEVICE_NOR: printf("NOR Boot");