| Message ID | 20191208222852.5506-3-lukas.auer@aisec.fraunhofer.de |
|---|---|
| State | Accepted |
| Commit | 8b3e97badf97d6e399014fb4a152031f8a0c94ba |
| Delegated to: | Andes |
| Headers | show |
| Series | Fixes for RISC-V U-Boot SPL / OpenSBI boot flow | expand |
> From: Lukas Auer [mailto:lukas.auer@aisec.fraunhofer.de] > Sent: Monday, December 09, 2019 6:29 AM > To: u-boot@lists.denx.de > Cc: Rick Jian-Zhi Chen(陳建志); Bin Meng; Anup Patel; Lukas Auer; Anup Patel; Atish Patra; Daniel Schwierzeck; Simon Glass > Subject: [PATCH v2 2/4] riscv: add functions for reading the IPI status > > Add the function riscv_get_ipi() for reading the pending status of IPIs. > The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). > > Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> > --- > > Changes in v2: > - Use the pending register instead of the claim register in the Andes PLIC implementation > Reviewed-by: Rick Chen <rick@andestech.com> > arch/riscv/lib/andes_plic.c | 11 +++++++++++ > arch/riscv/lib/sbi_ipi.c | 11 +++++++++++ > arch/riscv/lib/sifive_clint.c | 9 +++++++++ > arch/riscv/lib/smp.c | 12 ++++++++++++ > 4 files changed, 43 insertions(+) > > diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c index 28568e4e2b..42bda9b759 100644 > --- a/arch/riscv/lib/andes_plic.c > +++ b/arch/riscv/lib/andes_plic.c > @@ -114,6 +114,17 @@ int riscv_clear_ipi(int hart) > return 0; > } > > +int riscv_get_ipi(int hart, int *pending) { > + PLIC_BASE_GET(); > + > + *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic, > + gd->arch.boot_hart)); > + *pending = !!(*pending & SEND_IPI_TO_HART(hart)); > + > + return 0; > +} > + > static const struct udevice_id andes_plic_ids[] = { > { .compatible = "riscv,plic1", .data = RISCV_SYSCON_PLIC }, > { } > diff --git a/arch/riscv/lib/sbi_ipi.c b/arch/riscv/lib/sbi_ipi.c index 170346da68..9a698ce74e 100644 > --- a/arch/riscv/lib/sbi_ipi.c > +++ b/arch/riscv/lib/sbi_ipi.c > @@ -23,3 +23,14 @@ int riscv_clear_ipi(int hart) > > return 0; > } > + > +int riscv_get_ipi(int hart, int *pending) { > + /* > + * The SBI does not support reading the IPI status. We always return 0 > + * to indicate that no IPI is pending. > + */ > + *pending = 0; > + > + return 0; > +} > diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/sifive_clint.c index d24e0d585b..d7899d16d7 100644 > --- a/arch/riscv/lib/sifive_clint.c > +++ b/arch/riscv/lib/sifive_clint.c > @@ -71,6 +71,15 @@ int riscv_clear_ipi(int hart) > return 0; > } > > +int riscv_get_ipi(int hart, int *pending) { > + CLINT_BASE_GET(); > + > + *pending = readl((void __iomem *)MSIP_REG(gd->arch.clint, hart)); > + > + return 0; > +} > + > static const struct udevice_id sifive_clint_ids[] = { > { .compatible = "riscv,clint0", .data = RISCV_SYSCON_CLINT }, > { } > diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c index 705437862a..188a7e34bd 100644 > --- a/arch/riscv/lib/smp.c > +++ b/arch/riscv/lib/smp.c > @@ -32,6 +32,18 @@ extern int riscv_send_ipi(int hart); > */ > extern int riscv_clear_ipi(int hart); > > +/** > + * riscv_get_ipi() - Get status of inter-processor interrupt (IPI) > + * > + * Platform code must provide this function. > + * > + * @hart: Hart ID of hart to be checked > + * @pending: Pointer to variable with result of the check, > + * 1 if IPI is pending, 0 otherwise > + * @return 0 if OK, -ve on error > + */ > +extern int riscv_get_ipi(int hart, int *pending); > + > static int send_ipi_many(struct ipi_data *ipi) { > ofnode node, cpus; > -- > 2.21.0 >
diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c index 28568e4e2b..42bda9b759 100644 --- a/arch/riscv/lib/andes_plic.c +++ b/arch/riscv/lib/andes_plic.c @@ -114,6 +114,17 @@ int riscv_clear_ipi(int hart) return 0; } +int riscv_get_ipi(int hart, int *pending) +{ + PLIC_BASE_GET(); + + *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic, + gd->arch.boot_hart)); + *pending = !!(*pending & SEND_IPI_TO_HART(hart)); + + return 0; +} + static const struct udevice_id andes_plic_ids[] = { { .compatible = "riscv,plic1", .data = RISCV_SYSCON_PLIC }, { } diff --git a/arch/riscv/lib/sbi_ipi.c b/arch/riscv/lib/sbi_ipi.c index 170346da68..9a698ce74e 100644 --- a/arch/riscv/lib/sbi_ipi.c +++ b/arch/riscv/lib/sbi_ipi.c @@ -23,3 +23,14 @@ int riscv_clear_ipi(int hart) return 0; } + +int riscv_get_ipi(int hart, int *pending) +{ + /* + * The SBI does not support reading the IPI status. We always return 0 + * to indicate that no IPI is pending. + */ + *pending = 0; + + return 0; +} diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/sifive_clint.c index d24e0d585b..d7899d16d7 100644 --- a/arch/riscv/lib/sifive_clint.c +++ b/arch/riscv/lib/sifive_clint.c @@ -71,6 +71,15 @@ int riscv_clear_ipi(int hart) return 0; } +int riscv_get_ipi(int hart, int *pending) +{ + CLINT_BASE_GET(); + + *pending = readl((void __iomem *)MSIP_REG(gd->arch.clint, hart)); + + return 0; +} + static const struct udevice_id sifive_clint_ids[] = { { .compatible = "riscv,clint0", .data = RISCV_SYSCON_CLINT }, { } diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c index 705437862a..188a7e34bd 100644 --- a/arch/riscv/lib/smp.c +++ b/arch/riscv/lib/smp.c @@ -32,6 +32,18 @@ extern int riscv_send_ipi(int hart); */ extern int riscv_clear_ipi(int hart); +/** + * riscv_get_ipi() - Get status of inter-processor interrupt (IPI) + * + * Platform code must provide this function. + * + * @hart: Hart ID of hart to be checked + * @pending: Pointer to variable with result of the check, + * 1 if IPI is pending, 0 otherwise + * @return 0 if OK, -ve on error + */ +extern int riscv_get_ipi(int hart, int *pending); + static int send_ipi_many(struct ipi_data *ipi) { ofnode node, cpus;
Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> --- Changes in v2: - Use the pending register instead of the claim register in the Andes PLIC implementation arch/riscv/lib/andes_plic.c | 11 +++++++++++ arch/riscv/lib/sbi_ipi.c | 11 +++++++++++ arch/riscv/lib/sifive_clint.c | 9 +++++++++ arch/riscv/lib/smp.c | 12 ++++++++++++ 4 files changed, 43 insertions(+)