| Message ID | 20191202223421.3995-1-s-anna@ti.com |
|---|---|
| State | Accepted |
| Commit | 1045ff4d1af9e3e8a2ad4cf04a7263d49e90cfa7 |
| Delegated to: | Tom Rini |
| Headers | show |
| Series | [U-Boot] ARM: DRA7: Fixup DSP OPP_HIGH clock rate on DRA76P/DRA77P SoCs | expand |
On 03/12/19 4:04 AM, Suman Anna wrote: > The commit 1b42ab3eda8a ("ARM: DRA7: Fixup DSPEVE, IVA and GPU clock > frequencies based on OPP") added the core logic to update the kernel > device-tree blob to adjust the DSP, IVA and GPU DPLL clocks based on > a one-time OPP choice selected in U-Boot for most of the DRA7xx/AM57xx > family of SoCs. > > The DSPs on DRA76xP/DRA77xP SoCs (DRA76x ACD package SoCs) though > provide a higher performance and can run at a higher clock frequency > of 850 MHz at OPP_HIGH instead of 750 MHz. Fix up the logic to use the > correct clock rates on these SoCs. Note that this higher clock rate is > not applicable to other Jacinto 6 Plus SoCs (DRA75xP/DRA74xP SoCs or > AM574x SoCs) that follow the ABZ package. > > Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Thanks and regards, Lokesh > --- > arch/arm/mach-omap2/omap5/fdt.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/arch/arm/mach-omap2/omap5/fdt.c b/arch/arm/mach-omap2/omap5/fdt.c > index 8dee555c10c6..5ba8806dd744 100644 > --- a/arch/arm/mach-omap2/omap5/fdt.c > +++ b/arch/arm/mach-omap2/omap5/fdt.c > @@ -180,6 +180,14 @@ u32 dra7_opp_dsp_clk_rates[NUM_OPPS][OPP_DSP_CLK_NUM] = { > {750000000, 750000000, 500000000}, /* OPP_HIGH */ > }; > > +/* DSP clock rates on DRA76x ACD-package based SoCs */ > +u32 dra76_opp_dsp_clk_rates[NUM_OPPS][OPP_DSP_CLK_NUM] = { > + {}, /* OPP_LOW */ > + {600000000, 600000000, 400000000}, /* OPP_NOM */ > + {700000000, 700000000, 466666667}, /* OPP_OD */ > + {850000000, 850000000, 566666667}, /* OPP_HIGH */ > +}; > + > /* IVA voltage domain */ > u32 dra7_opp_iva_clk_rates[NUM_OPPS][OPP_IVA_CLK_NUM] = { > {}, /* OPP_LOW */ > @@ -257,6 +265,10 @@ static void ft_opp_clock_fixups(void *fdt, bd_t *bd) > /* fixup DSP clocks */ > clk_names = dra7_opp_dsp_clk_names; > clk_rates = dra7_opp_dsp_clk_rates[get_voltrail_opp(VOLT_EVE)]; > + /* adjust for higher OPP_HIGH clock rate on DRA76xP/DRA77xP SoCs */ > + if (is_dra76x_acd()) > + clk_rates = dra76_opp_dsp_clk_rates[get_voltrail_opp(VOLT_EVE)]; > + > ret = ft_fixup_clocks(fdt, clk_names, clk_rates, OPP_DSP_CLK_NUM); > if (ret) { > printf("ft_fixup_clocks failed for DSP voltage domain: %s\n", >
On Mon, Dec 02, 2019 at 04:34:21PM -0600, Suman Anna wrote: > The commit 1b42ab3eda8a ("ARM: DRA7: Fixup DSPEVE, IVA and GPU clock > frequencies based on OPP") added the core logic to update the kernel > device-tree blob to adjust the DSP, IVA and GPU DPLL clocks based on > a one-time OPP choice selected in U-Boot for most of the DRA7xx/AM57xx > family of SoCs. > > The DSPs on DRA76xP/DRA77xP SoCs (DRA76x ACD package SoCs) though > provide a higher performance and can run at a higher clock frequency > of 850 MHz at OPP_HIGH instead of 750 MHz. Fix up the logic to use the > correct clock rates on these SoCs. Note that this higher clock rate is > not applicable to other Jacinto 6 Plus SoCs (DRA75xP/DRA74xP SoCs or > AM574x SoCs) that follow the ABZ package. > > Signed-off-by: Suman Anna <s-anna@ti.com> > Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Applied to u-boot/master, thanks!
diff --git a/arch/arm/mach-omap2/omap5/fdt.c b/arch/arm/mach-omap2/omap5/fdt.c index 8dee555c10c6..5ba8806dd744 100644 --- a/arch/arm/mach-omap2/omap5/fdt.c +++ b/arch/arm/mach-omap2/omap5/fdt.c @@ -180,6 +180,14 @@ u32 dra7_opp_dsp_clk_rates[NUM_OPPS][OPP_DSP_CLK_NUM] = { {750000000, 750000000, 500000000}, /* OPP_HIGH */ }; +/* DSP clock rates on DRA76x ACD-package based SoCs */ +u32 dra76_opp_dsp_clk_rates[NUM_OPPS][OPP_DSP_CLK_NUM] = { + {}, /* OPP_LOW */ + {600000000, 600000000, 400000000}, /* OPP_NOM */ + {700000000, 700000000, 466666667}, /* OPP_OD */ + {850000000, 850000000, 566666667}, /* OPP_HIGH */ +}; + /* IVA voltage domain */ u32 dra7_opp_iva_clk_rates[NUM_OPPS][OPP_IVA_CLK_NUM] = { {}, /* OPP_LOW */ @@ -257,6 +265,10 @@ static void ft_opp_clock_fixups(void *fdt, bd_t *bd) /* fixup DSP clocks */ clk_names = dra7_opp_dsp_clk_names; clk_rates = dra7_opp_dsp_clk_rates[get_voltrail_opp(VOLT_EVE)]; + /* adjust for higher OPP_HIGH clock rate on DRA76xP/DRA77xP SoCs */ + if (is_dra76x_acd()) + clk_rates = dra76_opp_dsp_clk_rates[get_voltrail_opp(VOLT_EVE)]; + ret = ft_fixup_clocks(fdt, clk_names, clk_rates, OPP_DSP_CLK_NUM); if (ret) { printf("ft_fixup_clocks failed for DSP voltage domain: %s\n",
The commit 1b42ab3eda8a ("ARM: DRA7: Fixup DSPEVE, IVA and GPU clock frequencies based on OPP") added the core logic to update the kernel device-tree blob to adjust the DSP, IVA and GPU DPLL clocks based on a one-time OPP choice selected in U-Boot for most of the DRA7xx/AM57xx family of SoCs. The DSPs on DRA76xP/DRA77xP SoCs (DRA76x ACD package SoCs) though provide a higher performance and can run at a higher clock frequency of 850 MHz at OPP_HIGH instead of 750 MHz. Fix up the logic to use the correct clock rates on these SoCs. Note that this higher clock rate is not applicable to other Jacinto 6 Plus SoCs (DRA75xP/DRA74xP SoCs or AM574x SoCs) that follow the ABZ package. Signed-off-by: Suman Anna <s-anna@ti.com> --- arch/arm/mach-omap2/omap5/fdt.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)