From patchwork Mon Dec 2 08:54:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 1203014 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="P2C2aoi8"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47RJqk2xpgz9sPT for ; Mon, 2 Dec 2019 19:56:02 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 0ABBFC21DFD; Mon, 2 Dec 2019 08:55:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 967FBC21D8A; Mon, 2 Dec 2019 08:54:43 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 69361C21D9A; Mon, 2 Dec 2019 08:54:35 +0000 (UTC) Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lists.denx.de (Postfix) with ESMTPS id 569BBC21DB3 for ; Mon, 2 Dec 2019 08:54:31 +0000 (UTC) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id xB28sT98073493; Mon, 2 Dec 2019 02:54:29 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1575276869; bh=DOR69gbqYB/li1NAp2gsFUAjYuZkzho88zlGY4d0wPA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=P2C2aoi8XPzZ93Nlr9bDwTqlWX67Jbxo57pkJZB8KOxT9Q6o4vmYI8CFiGKUM8vob uRmpSMzjN5eK/im2CslylpBKNMPp9YhQo7i83DE33SXiYAn+ZRVrOHUyEMK3mq58tj EE99155kljQDpdnySPbuj2Q1NdNDxIQsfiatSHz4= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id xB28sTcl110946; Mon, 2 Dec 2019 02:54:29 -0600 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 2 Dec 2019 02:54:29 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 2 Dec 2019 02:54:29 -0600 Received: from a0132425.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id xB28sGZ6098983; Mon, 2 Dec 2019 02:54:27 -0600 From: Vignesh Raghavendra To: Tom Rini Date: Mon, 2 Dec 2019 14:24:39 +0530 Message-ID: <20191202085444.29848-6-vigneshr@ti.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191202085444.29848-1-vigneshr@ti.com> References: <20191202085444.29848-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH RESEND v2 05/10] dma: ti: k3-udma: Remove coherency check for cache ops X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Remove redundant coherency checks before calling cache ops in UDMA driver. This is now handled in arch specific cache operation implementation based on Kconfig option Signed-off-by: Vignesh Raghavendra --- drivers/dma/ti/k3-udma.c | 49 +++++++++++++--------------------------- 1 file changed, 16 insertions(+), 33 deletions(-) diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index 2f82ab0955a4..ee4bc531cb50 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -93,7 +93,6 @@ struct udma_dev { u32 psil_base; u32 ch_count; - bool is_coherent; }; struct udma_chan { @@ -274,11 +273,6 @@ static inline bool udma_is_chan_running(struct udma_chan *uc) return false; } -static int udma_is_coherent(struct udma_chan *uc) -{ - return uc->ud->is_coherent; -} - static int udma_pop_from_ring(struct udma_chan *uc, dma_addr_t *addr) { struct k3_nav_ring *ring = NULL; @@ -1305,7 +1299,6 @@ static int udma_probe(struct udevice *dev) return ret; } - ud->is_coherent = dev_read_bool(dev, "dma-coherent"); tisci_rm->tisci_udmap_ops = &tisci_rm->tisci->ops.rm_udmap_ops; tisci_rm->tisci_psil_ops = &tisci_rm->tisci->ops.rm_psil_ops; @@ -1453,11 +1446,9 @@ static int *udma_prep_dma_memcpy(struct udma_chan *uc, dma_addr_t dest, cppi5_tr_csf_set(&tr_req[num_tr - 1].flags, CPPI5_TR_CSF_EOP); - if (!udma_is_coherent(uc)) { - flush_dcache_range((u64)tr_desc, - ALIGN((u64)tr_desc + desc_size, - ARCH_DMA_MINALIGN)); - } + flush_dcache_range((u64)tr_desc, + ALIGN((u64)tr_desc + desc_size, + ARCH_DMA_MINALIGN)); k3_nav_ringacc_ring_push(uc->tchan->t_ring, &tr_desc); @@ -1622,14 +1613,12 @@ static int udma_send(struct dma *dma, void *src, size_t len, void *metadata) cppi5_hdesc_set_pkttype(desc_tx, packet_data.pkt_type); cppi5_desc_set_tags_ids(&desc_tx->hdr, 0, packet_data.dest_tag); - if (!udma_is_coherent(uc)) { - flush_dcache_range((u64)dma_src, - ALIGN((u64)dma_src + len, - ARCH_DMA_MINALIGN)); - flush_dcache_range((u64)desc_tx, - ALIGN((u64)desc_tx + uc->hdesc_size, - ARCH_DMA_MINALIGN)); - } + flush_dcache_range((u64)dma_src, + ALIGN((u64)dma_src + len, + ARCH_DMA_MINALIGN)); + flush_dcache_range((u64)desc_tx, + ALIGN((u64)desc_tx + uc->hdesc_size, + ARCH_DMA_MINALIGN)); ret = k3_nav_ringacc_ring_push(uc->tchan->t_ring, &uc->desc_tx); if (ret) { @@ -1673,19 +1662,15 @@ static int udma_receive(struct dma *dma, void **dst, void *metadata) } /* invalidate cache data */ - if (!udma_is_coherent(uc)) { - invalidate_dcache_range((ulong)desc_rx, - (ulong)(desc_rx + uc->hdesc_size)); - } + invalidate_dcache_range((ulong)desc_rx, + (ulong)(desc_rx + uc->hdesc_size)); cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); pkt_len = cppi5_hdesc_get_pktlen(desc_rx); /* invalidate cache data */ - if (!udma_is_coherent(uc)) { - invalidate_dcache_range((ulong)buf_dma, - (ulong)(buf_dma + buf_dma_len)); - } + invalidate_dcache_range((ulong)buf_dma, + (ulong)(buf_dma + buf_dma_len)); cppi5_desc_get_tags_ids(&desc_rx->hdr, &port_id, NULL); @@ -1790,11 +1775,9 @@ int udma_prepare_rcv_buf(struct dma *dma, void *dst, size_t size) cppi5_hdesc_set_pktlen(desc_rx, size); cppi5_hdesc_attach_buf(desc_rx, dma_dst, size, dma_dst, size); - if (!udma_is_coherent(uc)) { - flush_dcache_range((u64)desc_rx, - ALIGN((u64)desc_rx + uc->hdesc_size, - ARCH_DMA_MINALIGN)); - } + flush_dcache_range((u64)desc_rx, + ALIGN((u64)desc_rx + uc->hdesc_size, + ARCH_DMA_MINALIGN)); k3_nav_ringacc_ring_push(uc->rchan->fd_ring, &desc_rx);