From patchwork Mon Dec 2 08:54:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 1203024 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="ZaixmvGv"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47RJv34tmcz9sPJ for ; Mon, 2 Dec 2019 19:58:55 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 556DEC21DB3; Mon, 2 Dec 2019 08:56:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 83444C21DA2; Mon, 2 Dec 2019 08:56:24 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 0D95FC21C57; Mon, 2 Dec 2019 08:54:42 +0000 (UTC) Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lists.denx.de (Postfix) with ESMTPS id F158FC21DA1 for ; Mon, 2 Dec 2019 08:54:38 +0000 (UTC) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id xB28sbXY118645; Mon, 2 Dec 2019 02:54:37 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1575276877; bh=xhTZIoUNpH0UsZvBJIaRfgoW2Z3K7ebUyIyz22Y4ejs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ZaixmvGvpeCx1YXkhCYnKnKwBMp2QnRsQTtilgzmS9G8/Iyz8ANLMiKBE9YZU3tti irkJf993x//XEm4CygsFkkODokaREkIVxnUCLtep2wWClCSerxt/l5rQnsk9YBajDl uJVntwWQX+uAE2rem19PlKL3HJgxLfsxMtUPftlo= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xB28sbxH121482 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 2 Dec 2019 02:54:37 -0600 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 2 Dec 2019 02:54:37 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 2 Dec 2019 02:54:37 -0600 Received: from a0132425.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id xB28sGZA098983; Mon, 2 Dec 2019 02:54:35 -0600 From: Vignesh Raghavendra To: Tom Rini Date: Mon, 2 Dec 2019 14:24:43 +0530 Message-ID: <20191202085444.29848-10-vigneshr@ti.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191202085444.29848-1-vigneshr@ti.com> References: <20191202085444.29848-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH RESEND v2 09/10] dma: ti: k3-udma: Fix build warnings when building for 32 bit platforms X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Cast pointers properly so as to avoid warnings when driver is built for 32 bit platforms Signed-off-by: Vignesh Raghavendra --- drivers/dma/ti/k3-udma.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index 33b1d7880bed..03c48c9d1ee2 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -1454,8 +1454,8 @@ static int *udma_prep_dma_memcpy(struct udma_chan *uc, dma_addr_t dest, cppi5_tr_csf_set(&tr_req[num_tr - 1].flags, CPPI5_TR_CSF_EOP); - flush_dcache_range((u64)tr_desc, - ALIGN((u64)tr_desc + desc_size, + flush_dcache_range((unsigned long)tr_desc, + ALIGN((unsigned long)tr_desc + desc_size, ARCH_DMA_MINALIGN)); udma_push_to_ring(uc->tchan->t_ring, tr_desc); @@ -1621,11 +1621,11 @@ static int udma_send(struct dma *dma, void *src, size_t len, void *metadata) cppi5_hdesc_set_pkttype(desc_tx, packet_data.pkt_type); cppi5_desc_set_tags_ids(&desc_tx->hdr, 0, packet_data.dest_tag); - flush_dcache_range((u64)dma_src, - ALIGN((u64)dma_src + len, + flush_dcache_range((unsigned long)dma_src, + ALIGN((unsigned long)dma_src + len, ARCH_DMA_MINALIGN)); - flush_dcache_range((u64)desc_tx, - ALIGN((u64)desc_tx + uc->hdesc_size, + flush_dcache_range((unsigned long)desc_tx, + ALIGN((unsigned long)desc_tx + uc->hdesc_size, ARCH_DMA_MINALIGN)); ret = udma_push_to_ring(uc->tchan->t_ring, uc->desc_tx); @@ -1783,8 +1783,8 @@ int udma_prepare_rcv_buf(struct dma *dma, void *dst, size_t size) cppi5_hdesc_set_pktlen(desc_rx, size); cppi5_hdesc_attach_buf(desc_rx, dma_dst, size, dma_dst, size); - flush_dcache_range((u64)desc_rx, - ALIGN((u64)desc_rx + uc->hdesc_size, + flush_dcache_range((unsigned long)desc_rx, + ALIGN((unsigned long)desc_rx + uc->hdesc_size, ARCH_DMA_MINALIGN)); udma_push_to_ring(uc->rchan->fd_ring, desc_rx);