From patchwork Mon Nov 18 21:04:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 1196974 X-Patchwork-Delegate: joe.hershberger@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="we7Ysylt"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47H20b71VFz9sP4 for ; Tue, 19 Nov 2019 08:19:59 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id B1129C21E18; Mon, 18 Nov 2019 21:19:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B800FC21E42; Mon, 18 Nov 2019 21:06:28 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 71C10C21E4E; Mon, 18 Nov 2019 21:06:27 +0000 (UTC) Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lists.denx.de (Postfix) with ESMTPS id E7A33C21E42 for ; Mon, 18 Nov 2019 21:05:16 +0000 (UTC) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id xAIL5DXV035104; Mon, 18 Nov 2019 15:05:13 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1574111113; bh=PxMXp6r6mNZtbMKQZab1k44shahxuo4TKmmgzn7qVR4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=we7YsyltTM9jBE52SC1JPO4ZEC95zxR7raJqwGF7N7aOzwluWgk4SHauuAAIqMPqg FL1jqoIBlNsVbpv8xuniOLkMosEPgE+UvCTYcFawXCiJy3me4nh/RPR15keOKVCOVq Nt1Pd0MBtcJnSnV5/pSrN6+ELprCp3Fc5I/9EC7Y= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xAIL5DLT090060 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 18 Nov 2019 15:05:13 -0600 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 18 Nov 2019 15:05:13 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 18 Nov 2019 15:05:13 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id xAIL5Cfg035979; Mon, 18 Nov 2019 15:05:12 -0600 From: Grygorii Strashko To: Joe Hershberger Date: Mon, 18 Nov 2019 23:04:43 +0200 Message-ID: <20191118210447.7433-5-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191118210447.7433-1-grygorii.strashko@ti.com> References: <20191118210447.7433-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: Tom Rini , Michal Simek , u-boot@lists.denx.de, Trent Piepho Subject: [U-Boot] [PATCH 4/8] net: phy: dp83867: Add ability to disable output clock X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Based on commit 13c83cf8af0d ("net: phy: dp83867: Add ability to disable output clock") of mainline linux kernel. Generally, the output clock pin is only used for testing and only serves as a source of RF noise after this. It could be used to daisy-chain PHYs, but this is uncommon. Since the PHY can disable the output, make doing so an option. I do this by adding another enumeration to the allowed values of ti,clk-output-sel. The code was not using the value DP83867_CLK_O_SEL_REF_CLK as one might expect: to select the REF_CLK as the output. Rather it meant "keep clock output setting as is", which, depending on PHY strapping, might not be outputting REF_CLK. Change this so DP83867_CLK_O_SEL_REF_CLK means enable REF_CLK output. Omitting the property will leave the setting as is (which was the previous behavior in this case). Out of range values were silently converted into DP83867_CLK_O_SEL_REF_CLK. Change this so they generate an error. Signed-off-by: Grygorii Strashko Acked-by: Joe Hershberger --- drivers/net/phy/dp83867.c | 53 ++++++++++++++++++++++++++------------- 1 file changed, 36 insertions(+), 17 deletions(-) diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c index 8dc2163342..cd3c1c596a 100644 --- a/drivers/net/phy/dp83867.c +++ b/drivers/net/phy/dp83867.c @@ -83,6 +83,7 @@ #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f +#define DP83867_IO_MUX_CFG_CLK_O_DISABLE BIT(6) #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8 #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK \ GENMASK(0x1f, DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT) @@ -103,6 +104,7 @@ struct dp83867_private { int io_impedance; bool rxctrl_strap_quirk; int port_mirroring; + bool set_clk_output; unsigned int clk_output_sel; }; @@ -134,16 +136,28 @@ static int dp83867_of_init(struct phy_device *phydev) { struct dp83867_private *dp83867 = phydev->priv; ofnode node; - u16 val; + int ret; node = phy_get_ofnode(phydev); if (!ofnode_valid(node)) return -EINVAL; - /* Keep the default value if ti,clk-output-sel is not set */ - dp83867->clk_output_sel = - ofnode_read_u32_default(node, "ti,clk-output-sel", - DP83867_CLK_O_SEL_REF_CLK); + /* Optional configuration */ + ret = ofnode_read_u32(node, "ti,clk-output-sel", + &dp83867->clk_output_sel); + /* If not set, keep default */ + if (!ret) { + dp83867->set_clk_output = true; + /* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or + * DP83867_CLK_O_SEL_OFF. + */ + if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK && + dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) { + pr_debug("ti,clk-output-sel value %u out of range\n", + dp83867->clk_output_sel); + return -EINVAL; + } + } if (ofnode_read_bool(node, "ti,max-output-impedance")) dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX; @@ -170,18 +184,6 @@ static int dp83867_of_init(struct phy_device *phydev) if (ofnode_read_bool(node, "enet-phy-lane-no-swap")) dp83867->port_mirroring = DP83867_PORT_MIRRORING_DIS; - - /* Clock output selection if muxing property is set */ - if (dp83867->clk_output_sel != DP83867_CLK_O_SEL_REF_CLK) { - val = phy_read_mmd(phydev, DP83867_DEVADDR, - DP83867_IO_MUX_CFG); - val &= ~DP83867_IO_MUX_CFG_CLK_O_SEL_MASK; - val |= (dp83867->clk_output_sel << - DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT); - phy_write_mmd(phydev, DP83867_DEVADDR, - DP83867_IO_MUX_CFG, val); - } - return 0; } #else @@ -313,6 +315,23 @@ static int dp83867_config(struct phy_device *phydev) if (dp83867->port_mirroring != DP83867_PORT_MIRRORING_KEEP) dp83867_config_port_mirroring(phydev); + /* Clock output selection if muxing property is set */ + if (dp83867->set_clk_output) { + val = phy_read_mmd(phydev, DP83867_DEVADDR, + DP83867_IO_MUX_CFG); + + if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) { + val |= DP83867_IO_MUX_CFG_CLK_O_DISABLE; + } else { + val &= ~(DP83867_IO_MUX_CFG_CLK_O_SEL_MASK | + DP83867_IO_MUX_CFG_CLK_O_DISABLE); + val |= dp83867->clk_output_sel << + DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT; + } + phy_write_mmd(phydev, DP83867_DEVADDR, + DP83867_IO_MUX_CFG, val); + } + genphy_config_aneg(phydev); return 0;