From patchwork Thu Oct 31 10:54:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yangbo Lu X-Patchwork-Id: 1187353 X-Patchwork-Delegate: van.freenix@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nxp.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 473j1s304Pz9sP4 for ; Thu, 31 Oct 2019 21:56:49 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 1D771C21EC5; Thu, 31 Oct 2019 10:55:00 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 04C51C21F27; Thu, 31 Oct 2019 10:54:43 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 308BBC21EFF; Thu, 31 Oct 2019 10:54:11 +0000 (UTC) Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) by lists.denx.de (Postfix) with ESMTPS id 6B0CDC21ECE for ; Thu, 31 Oct 2019 10:54:09 +0000 (UTC) Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 3BF632002EA; Thu, 31 Oct 2019 11:54:09 +0100 (CET) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 6DB702004E2; Thu, 31 Oct 2019 11:54:07 +0100 (CET) Received: from localhost.localdomain (mega.ap.freescale.net [10.192.208.232]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 1A97D402A2; Thu, 31 Oct 2019 18:54:03 +0800 (SGT) From: Yangbo Lu To: u-boot@lists.denx.de, Peng Fan Date: Thu, 31 Oct 2019 18:54:25 +0800 Message-Id: <20191031105426.5672-7-yangbo.lu@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191031105426.5672-1-yangbo.lu@nxp.com> References: <20191031105426.5672-1-yangbo.lu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Subject: [U-Boot] [PATCH 6/7] mmc: fsl_esdhc: always check write protect state X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The QorIQ eSDHC on all platforms supports checking write protect state through register bit. So check it always. Signed-off-by: Yangbo Lu --- drivers/mmc/fsl_esdhc.c | 15 ++++----------- include/fsl_esdhc.h | 1 - 2 files changed, 4 insertions(+), 12 deletions(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 25a8fe3..bdc0ca6 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -75,7 +75,6 @@ struct fsl_esdhc_plat { * @mmc: mmc * Following is used when Driver Model is enabled for MMC * @dev: pointer for the device - * @wp_enable: 1: enable checking wp; 0: no check * @cd_gpio: gpio for card detection * @wp_gpio: gpio for write protection */ @@ -88,7 +87,6 @@ struct fsl_esdhc_priv { struct mmc *mmc; #endif struct udevice *dev; - int wp_enable; }; /* Return the XFERTYP flags for a given command and data packet */ @@ -231,12 +229,10 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, #endif if (wml_value > WML_WR_WML_MAX) wml_value = WML_WR_WML_MAX_VAL; - if (priv->wp_enable) { - if ((esdhc_read32(®s->prsstat) & - PRSSTAT_WPSPL) == 0) { - printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); - return -ETIMEDOUT; - } + + if (!(esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL)) { + printf("Can not write to locked SD card.\n"); + return -EINVAL; } esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, @@ -722,7 +718,6 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base); priv->sdhc_clk = cfg->sdhc_clk; - priv->wp_enable = cfg->wp_enable; mmc_cfg = &plat->cfg; @@ -862,8 +857,6 @@ static int fsl_esdhc_probe(struct udevice *dev) #endif priv->dev = dev; - priv->wp_enable = 1; - if (IS_ENABLED(CONFIG_CLK)) { /* Assigned clock already set clock */ ret = clk_get_by_name(dev, "per", &priv->per_clk); diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index a015df1..8e8cd2c 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -168,7 +168,6 @@ struct fsl_esdhc_cfg { phys_addr_t esdhc_base; u32 sdhc_clk; u8 max_bus_width; - int wp_enable; int vs18_enable; /* Use 1.8V if set to 1 */ struct mmc_config cfg; };