| Message ID | 20191029210821.1954-3-suneelglinux@gmail.com |
|---|---|
| State | RFC |
| Delegated to: | Tom Rini |
| Headers | show |
| Series | arm: Introduce Marvell/Cavium OcteonTX | expand |
Hi Suneel, On Tue, 29 Oct 2019 at 14:08, Suneel Garapati <suneelglinux@gmail.com> wrote: > > From: Suneel Garapati <sgarapati@marvell.com> > > Increase MAX_PCI_REGIONS limit from 7 to 10. For some SoC's > like OcteonTX/TX2 where everything is on PCI bus there is > need for extra entries to support required peripherals. > > Signed-off-by: Suneel Garapati <sgarapati@marvell.com> > --- > include/pci.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/include/pci.h b/include/pci.h > index ff59ac0e69..0b14842285 100644 > --- a/include/pci.h > +++ b/include/pci.h > @@ -567,7 +567,7 @@ extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev, > extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev, > struct pci_config_table *); > > -#define MAX_PCI_REGIONS 7 > +#define MAX_PCI_REGIONS 10 This needs to be dynamic, with malloc() used to allocate the space in struct pci_controller, after calculating how many entries there are. The current scheme and your patch breaks x86 devices with limited pre-reloc memory. Regards, Simon
diff --git a/include/pci.h b/include/pci.h index ff59ac0e69..0b14842285 100644 --- a/include/pci.h +++ b/include/pci.h @@ -567,7 +567,7 @@ extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev, extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *); -#define MAX_PCI_REGIONS 7 +#define MAX_PCI_REGIONS 10 #define INDIRECT_TYPE_NO_PCIE_LINK 1