From patchwork Tue Oct 29 21:08:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suneel Garapati X-Patchwork-Id: 1186298 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="IJaRRe0V"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 472kpX1PkHz9sCJ for ; Wed, 30 Oct 2019 08:13:40 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id C64C5C21C51; Tue, 29 Oct 2019 21:10:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E9E07C21E2B; Tue, 29 Oct 2019 21:08:49 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 8B3FAC21E1A; Tue, 29 Oct 2019 21:08:41 +0000 (UTC) Received: from mail-pl1-f196.google.com (mail-pl1-f196.google.com [209.85.214.196]) by lists.denx.de (Postfix) with ESMTPS id 2A406C21E02 for ; Tue, 29 Oct 2019 21:08:36 +0000 (UTC) Received: by mail-pl1-f196.google.com with SMTP id q16so8046746pll.11 for ; Tue, 29 Oct 2019 14:08:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=x0233aHTFlWZVdgC2oXa1TBI0uGdR74inpUHnAvLBcY=; b=IJaRRe0VH5kfAeuNmvxxsl9xRbh8wDVbY7PglN3+7JMmA86k2a48wpbrLkx+kL/tEf FQJ/t5QtY+vxNFnZRvN+g7LF3vLMHebz0OksrLz/izjfl7bOc3FTpiaHtInhznKF7IFB D2WS3/6pxiExkE6Zmdi0WKub+f25W2Fru4stn2z2CHHeHo6frDOb4HHhK4uTN3afq26r l043PoWnkUaC7iE/E5+AYXohLqKxTGxOHlw72uP3R8usgEm4RH59q7b2ymuKL4HXO+Q0 PLRh/mGdS0mA9w3lfccpyevr5k/NTStYMXdrO/QSBhOF3riHmMLY7x/j0S9GU+v3iJh9 jrGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=x0233aHTFlWZVdgC2oXa1TBI0uGdR74inpUHnAvLBcY=; b=H8SaYd/3clV7tUecXh+eC43UdUmDM7COUhymEDKtqSmRF5uaWzpifn+W3wOFppFZ7F 0uwx8FMVsKJn6Of160hNVjCnno0TGTG8VfnU9s7K8CGerwnD0+S7WkRxrUUc0zX2sGj2 O0uAkiPd824hAnOGLPRGjBqZjcUUhgnhBGpgBPZriH2/g5W5S05miZdJ2d7AAiEmGnSq ouyBxqXH2U5u5vsa81j6C9dkXR0stmO6Gh2ccfvRUiu05kLHBDQKZAq1GTtelVE/mPG2 jFXjSyf+cM9TnuFsKRgJJJqLSqD1+mBjtgQ41S91a0mC/NyZPo6RWjl2rd1ZsWARlviI xOEQ== X-Gm-Message-State: APjAAAXOWtRZg2Iws5pjsxMFZq1FqVh3qzA25KV8D9nXMUN8IvhKrM+h n6y+860k7ni7AP2zXw/NYoKAwXaC X-Google-Smtp-Source: APXvYqypfk43G1/2HKegWmgUOlOdRXDc8dzq+C73Gttl80AZDQ0Bahu/HJN8sek5ftDhiO7IEiS9fg== X-Received: by 2002:a17:902:9b86:: with SMTP id y6mr786315plp.84.1572383314514; Tue, 29 Oct 2019 14:08:34 -0700 (PDT) Received: from suneel.hsd1.ca.comcast.net ([2601:641:4000:c9c0:7044:5eef:7096:2413]) by smtp.gmail.com with ESMTPSA id q3sm131160pgj.54.2019.10.29.14.08.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2019 14:08:33 -0700 (PDT) From: Suneel Garapati To: u-boot Date: Tue, 29 Oct 2019 14:08:01 -0700 Message-Id: <20191029210821.1954-10-suneelglinux@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191029210821.1954-1-suneelglinux@gmail.com> References: <20191029210821.1954-1-suneelglinux@gmail.com> MIME-Version: 1.0 Cc: Tom Rini , Matthias Brugger , Joe Hershberger , Prasun Kapoor , Maen Suleiman , Chandrakala Chavva , Zi Shen Lim , Stefan Roese , Chris Packham Subject: [U-Boot] [RFC PATCH 09/29] drivers: pci-uclass: add VF map_bar support for Enhanced Allocation X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Suneel Garapati Makes dm_pci_map_bar API available for Virtual function PCI devices based on SR-IOV capability which support Enhanced Allocation. Signed-off-by: Suneel Garapati --- drivers/pci/pci-uclass.c | 46 +++++++++++++++++++++++++++++++++++----- include/pci.h | 3 +++ 2 files changed, 44 insertions(+), 5 deletions(-) diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 3be49c7115..f9823231b1 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -1359,13 +1359,19 @@ pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr, } static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, int flags, - int ea_off) + int ea_off, struct pci_child_platdata *pdata) { int ea_cnt, i, entry_size; int bar_id = (bar - PCI_BASE_ADDRESS_0) >> 2; u32 ea_entry; phys_addr_t addr; + /* In case of Virtual Function devices, device is Physical function, + * so pdata will point to required VF specific data. + */ + if (pdata->is_virtfn) + bar_id += PCI_EA_BEI_VF_BAR0; + /* EA capability structure header */ dm_pci_read_config32(dev, ea_off, &ea_entry); ea_cnt = (ea_entry >> 16) & PCI_EA_NUM_ENT_MASK; @@ -1388,6 +1394,26 @@ static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, int flags, addr |= ((u64)ea_entry) << 32; } + /* In case of Virtual Function devices using BAR + * base and size, add offset for VFn BAR(1, 2, 3...n) + */ + if (pdata->is_virtfn) { + size_t sz; + + /* MaxOffset, 1st DW */ + dm_pci_read_config32(dev, ea_off + 8, &ea_entry); + sz = ea_entry & PCI_EA_FIELD_MASK; + /* Fill up lower 2 bits */ + sz |= (~PCI_EA_FIELD_MASK); + if (ea_entry & PCI_EA_IS_64) { + /* MaxOffset 2nd DW */ + dm_pci_read_config32(dev, ea_off + 16, + &ea_entry); + sz |= ((u64)ea_entry) << 32; + } + addr += (pdata->virtid - 1) * (sz + 1); + } + /* size ignored for now */ return map_physmem(addr, 0, flags); } @@ -1400,17 +1426,27 @@ void *dm_pci_map_bar(struct udevice *dev, int bar, int flags) pci_addr_t pci_bus_addr; u32 bar_response; int ea_off; + struct udevice *udev = dev; + struct pci_child_platdata *pdata = dev_get_parent_platdata(dev); + + /* In case of Virtual Function devices, use PF udevice + * as EA capability is defined in Physical Function + */ + if (pdata->is_virtfn) + udev = pdata->pfdev; /* * if the function supports Enhanced Allocation use that instead of * BARs + * Incase of virtual functions, pdata will help read VF BEI + * and EA entry size. */ - ea_off = dm_pci_find_capability(dev, PCI_CAP_ID_EA); + ea_off = dm_pci_find_capability(udev, PCI_CAP_ID_EA); if (ea_off) - return dm_pci_map_ea_bar(dev, bar, flags, ea_off); + return dm_pci_map_ea_bar(udev, bar, flags, ea_off, pdata); /* read BAR address */ - dm_pci_read_config32(dev, bar, &bar_response); + dm_pci_read_config32(udev, bar, &bar_response); pci_bus_addr = (pci_addr_t)(bar_response & ~0xf); /* @@ -1419,7 +1455,7 @@ void *dm_pci_map_bar(struct udevice *dev, int bar, int flags) * linear mapping. In the future, this could read the BAR size * and pass that as the size if needed. */ - return dm_pci_bus_to_virt(dev, pci_bus_addr, flags, 0, MAP_NOCACHE); + return dm_pci_bus_to_virt(udev, pci_bus_addr, flags, 0, MAP_NOCACHE); } static int _dm_pci_find_next_capability(struct udevice *dev, u8 pos, int cap) diff --git a/include/pci.h b/include/pci.h index 1343d0e9fb..27819e86f5 100644 --- a/include/pci.h +++ b/include/pci.h @@ -465,6 +465,9 @@ #define PCI_EA_FIRST_ENT 4 /* First EA Entry in List */ #define PCI_EA_ES 0x00000007 /* Entry Size */ #define PCI_EA_BEI 0x000000f0 /* BAR Equivalent Indicator */ +/* 9-14 map to VF BARs 0-5 respectively */ +#define PCI_EA_BEI_VF_BAR0 9 +#define PCI_EA_BEI_VF_BAR5 14 /* Base, MaxOffset registers */ /* bit 0 is reserved */ #define PCI_EA_IS_64 0x00000002 /* 64-bit field flag */