From patchwork Mon Oct 21 10:09:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yangbo Lu X-Patchwork-Id: 1180445 X-Patchwork-Delegate: van.freenix@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nxp.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 46xXR305TTz9sCJ for ; Mon, 21 Oct 2019 21:08:46 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 944ABC21E16; Mon, 21 Oct 2019 10:08:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 73FBAC21C93; Mon, 21 Oct 2019 10:08:38 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id DD048C21D74; Mon, 21 Oct 2019 10:08:36 +0000 (UTC) Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by lists.denx.de (Postfix) with ESMTPS id 560B7C21D72 for ; Mon, 21 Oct 2019 10:08:36 +0000 (UTC) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 286E21A0889; Mon, 21 Oct 2019 12:08:36 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 5D92B1A0532; Mon, 21 Oct 2019 12:08:34 +0200 (CEST) Received: from localhost.localdomain (mega.ap.freescale.net [10.192.208.232]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 21BFE40320; Mon, 21 Oct 2019 18:08:32 +0800 (SGT) From: Yangbo Lu To: u-boot@lists.denx.de, Peng Fan Date: Mon, 21 Oct 2019 18:09:09 +0800 Message-Id: <20191021100909.3708-4-yangbo.lu@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191021100909.3708-1-yangbo.lu@nxp.com> References: <20191021100909.3708-1-yangbo.lu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Subject: [U-Boot] [PATCH 3/3] mmc: fsl_esdhc: drop i.MX DDR support code X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" A previous patch below adding DDR mode support was actually for i.MX platforms. Now i.MX eSDHC driver is fsl_esdhc_imx.c. For QorIQ eSDHC, it uses different process for DDR mode, and hasn't been supported. Let's drop DDR support code for i.MX in fsl_esdhc driver. 0e1bf61 mmc: fsl_esdhc: Add support for DDR mode Signed-off-by: Yangbo Lu --- drivers/mmc/fsl_esdhc.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 03c54c3..cd357ea 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -501,7 +501,6 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) struct fsl_esdhc *regs = priv->esdhc_regs; int div = 1; int pre_div = 2; - int ddr_pre_div = mmc->ddr_mode ? 2 : 1; unsigned int sdhc_clk = priv->sdhc_clk; u32 time_out; u32 value; @@ -510,10 +509,10 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) if (clock < mmc->cfg->f_min) clock = mmc->cfg->f_min; - while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256) + while (sdhc_clk / (16 * pre_div) > clock && pre_div < 256) pre_div *= 2; - while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16) + while (sdhc_clk / (div * pre_div) > clock && div < 16) div++; pre_div >>= 1; @@ -773,9 +772,6 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv, cfg->host_caps = MMC_MODE_4BIT; cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; -#ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE - cfg->host_caps |= MMC_MODE_DDR_52MHz; -#endif if (priv->bus_width > 0) { if (priv->bus_width < 8)