From patchwork Wed Oct 16 09:06:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Matwey V. Kornilov" X-Patchwork-Id: 1177703 X-Patchwork-Delegate: ykai007@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="HsepTQCT"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 46tRJj6DZpz9sP3 for ; Wed, 16 Oct 2019 20:07:33 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 8CF84C21DD4; Wed, 16 Oct 2019 09:06:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 9ABBEC21DB6; Wed, 16 Oct 2019 09:06:44 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 5E915C21D8A; Wed, 16 Oct 2019 09:06:27 +0000 (UTC) Received: from mail-lf1-f66.google.com (mail-lf1-f66.google.com [209.85.167.66]) by lists.denx.de (Postfix) with ESMTPS id 8744BC21D9A for ; Wed, 16 Oct 2019 09:06:24 +0000 (UTC) Received: by mail-lf1-f66.google.com with SMTP id c195so16798540lfg.9 for ; Wed, 16 Oct 2019 02:06:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TFO93xs79BJmQmISt7uOV9vuSSf3CwZZMfNXiewDRc4=; b=HsepTQCTeOXhs1Yd/Hevq5AsI+8sAFij2zrYkS64HU6j9KDXmk5tqzD0onT1iaWHMF 5Pvsr5X2D2CMSjinM+/OqsDsaKf2/Au1E4uPI0qdLv6bcpknZcZCe9Y+kLRmTC8tvIoY apOJzYJavTY5HfoYVUSG1yHLH+bhFA7JgrWZhQwkL6PAmNAj1PNaBgaIScNUujyh+8Y9 LqLXFeAdlfT60gJd5dh0M2AeFJGbnf1zelsNCVqOYNGHoIQdobMfulqvNv2bc2sfLPRX BXmmXiIu3ZWZPTNCI3ww0dqIMYpofuXqYaukOGoz9zf2S4G5gcvqi8EFLbNkKh2vzku/ lRqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TFO93xs79BJmQmISt7uOV9vuSSf3CwZZMfNXiewDRc4=; b=hh2kR95gjt+euKvcNJTHsarUv6DDbGZ439WnjlLfD2v1ijymeUpilcCwDAm6G7IsG2 tAwAj6wKeYQwi0Z/IVfk6FE/80fJRw3r5xajpR8i52eTV2TE306G3VTSRtxIiY7wyPaV D/46FaRb3vBcXkzAsEl7aTi++IOIwdzpvXDE068RW+CHLkbR10r4eshTF/6u3cSCQByY 6xgjRaLxJM1NckB3nLXc6KRU+mmImvi7Ui4i++vKILwS6fXF9EBF1NYkuARu2vmfzuFQ zgEy3R7w4iKr8/6Ih0xm8/c7pTjPqg7/MObmj4o35htSLwJkmylNj3UDmmrbze1NWxqL gRKg== X-Gm-Message-State: APjAAAVn2ito+xacyk5VlA448yq1iMfoUTMPCRLszrpNjlGNf8cIPJAj AcHgDnEr0DkLw1cs7ASC9GCEEXbZNno= X-Google-Smtp-Source: APXvYqyT3K6u+fBWPLW8d1sThlMXEL6Wnu4Qm97YEwlIBf1W3v58G/+aY4PGiQUxEq4Kk5faeP7nKA== X-Received: by 2002:ac2:4a83:: with SMTP id l3mr24265713lfp.73.1571216783143; Wed, 16 Oct 2019 02:06:23 -0700 (PDT) Received: from alpha.sai.msu.ru ([93.180.21.1]) by smtp.gmail.com with ESMTPSA id c18sm6974258ljd.27.2019.10.16.02.06.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 16 Oct 2019 02:06:22 -0700 (PDT) From: "Matwey V. Kornilov" To: u-boot@lists.denx.de Date: Wed, 16 Oct 2019 12:06:11 +0300 Message-Id: <20191016090612.11356-3-matwey.kornilov@gmail.com> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191016090612.11356-1-matwey.kornilov@gmail.com> References: <20191016090612.11356-1-matwey.kornilov@gmail.com> Cc: Albert Aribaud , "Matwey V. Kornilov" Subject: [U-Boot] [PATCH 2/3] rockchip: rk3328: use common struct sdram_cap_info for struct rk3328_sdram_channel X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Currently, struct sdram_cap_info and struct rk3328_sdram_channel have similar layouts. Signed-off-by: Matwey V. Kornilov --- arch/arm/include/asm/arch-rockchip/sdram_rk3328.h | 13 +--- drivers/ram/rockchip/sdram_rk3328.c | 90 +++++++++++------------ 2 files changed, 46 insertions(+), 57 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h index ea5f5bfd86..e09fecd376 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h @@ -411,18 +411,7 @@ struct rk3328_ddr_skew { }; struct rk3328_sdram_channel { - unsigned int rank; - unsigned int col; - /* 3:8bank, 2:4bank */ - unsigned int bk; - /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */ - unsigned int bw; - /* die buswidth, 2:32bit, 1:16bit, 0:8bit */ - unsigned int dbw; - unsigned int row_3_4; - unsigned int cs0_row; - unsigned int cs1_row; - unsigned int ddrconfig; + struct sdram_cap_info cap_info; struct rk3328_msch_timings noc_timings; }; diff --git a/drivers/ram/rockchip/sdram_rk3328.c b/drivers/ram/rockchip/sdram_rk3328.c index 59b1638785..c2537cc95d 100644 --- a/drivers/ram/rockchip/sdram_rk3328.c +++ b/drivers/ram/rockchip/sdram_rk3328.c @@ -223,12 +223,12 @@ static unsigned int calculate_ddrconfig(struct rk3328_sdram_params *sdram_params u32 i, tmp; u32 ddrconf = -1; - cs = sdram_ch.rank; - bw = sdram_ch.bw; - die_bw = sdram_ch.dbw; - col = sdram_ch.col; - row = sdram_ch.cs0_row; - bank = sdram_ch.bk; + cs = sdram_ch.cap_info.rank; + bw = sdram_ch.cap_info.bw; + die_bw = sdram_ch.cap_info.dbw; + col = sdram_ch.cap_info.col; + row = sdram_ch.cap_info.cs0_row; + bank = sdram_ch.cap_info.bk; if (sdram_params->base.dramtype == DDR4) { tmp = ((cs - 1) << 6) | ((row - 13) << 3) | (bw & 0x2) | die_bw; @@ -285,13 +285,13 @@ static void set_ctl_address_map(struct dram_info *dram, void __iomem *pctl_base = dram->pctl; copy_to_reg((u32 *)(pctl_base + DDR_PCTL2_ADDRMAP0), - &addrmap[sdram_ch.ddrconfig][0], 9 * 4); - if (sdram_params->base.dramtype == LPDDR3 && sdram_ch.row_3_4) + &addrmap[sdram_ch.cap_info.ddrconfig][0], 9 * 4); + if (sdram_params->base.dramtype == LPDDR3 && sdram_ch.cap_info.row_3_4) setbits_le32(pctl_base + DDR_PCTL2_ADDRMAP6, 1 << 31); - if (sdram_params->base.dramtype == DDR4 && sdram_ch.bw == 0x1) + if (sdram_params->base.dramtype == DDR4 && sdram_ch.cap_info.bw == 0x1) setbits_le32(pctl_base + DDR_PCTL2_PCCFG, 1 << 8); - if (sdram_ch.rank == 1) + if (sdram_ch.cap_info.rank == 1) clrsetbits_le32(pctl_base + DDR_PCTL2_ADDRMAP0, 0x1f, 0x1f); } @@ -378,7 +378,7 @@ static void phy_cfg(struct dram_info *dram, writel(sdram_params->phy_regs.phy[i][1], phy_base + sdram_params->phy_regs.phy[i][0]); } - if (sdram_ch.bw == 2) { + if (sdram_ch.cap_info.bw == 2) { clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 0xf << 4); } else { clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 3 << 4); @@ -585,18 +585,18 @@ static void dram_all_config(struct dram_info *dram, { u32 sys_reg = 0, tmp = 0; - set_ddrconfig(dram, sdram_ch.ddrconfig); + set_ddrconfig(dram, sdram_ch.cap_info.ddrconfig); sys_reg |= SYS_REG_ENC_DDRTYPE(sdram_params->base.dramtype); - sys_reg |= SYS_REG_ENC_ROW_3_4(sdram_ch.row_3_4, 0); - sys_reg |= SYS_REG_ENC_RANK(sdram_ch.rank, 0); - sys_reg |= SYS_REG_ENC_COL(sdram_ch.col, 0); - sys_reg |= SYS_REG_ENC_BK(sdram_ch.bk, 0); - SYS_REG_ENC_CS0_ROW(sdram_ch.cs0_row, sys_reg, tmp, 0); - if (sdram_ch.cs1_row) - SYS_REG_ENC_CS1_ROW(sdram_ch.cs1_row, sys_reg, tmp, 0); - sys_reg |= SYS_REG_ENC_BW(sdram_ch.bw, 0); - sys_reg |= SYS_REG_ENC_DBW(sdram_ch.dbw, 0); + sys_reg |= SYS_REG_ENC_ROW_3_4(sdram_ch.cap_info.row_3_4, 0); + sys_reg |= SYS_REG_ENC_RANK(sdram_ch.cap_info.rank, 0); + sys_reg |= SYS_REG_ENC_COL(sdram_ch.cap_info.col, 0); + sys_reg |= SYS_REG_ENC_BK(sdram_ch.cap_info.bk, 0); + SYS_REG_ENC_CS0_ROW(sdram_ch.cap_info.cs0_row, sys_reg, tmp, 0); + if (sdram_ch.cap_info.cs1_row) + SYS_REG_ENC_CS1_ROW(sdram_ch.cap_info.cs1_row, sys_reg, tmp, 0); + sys_reg |= SYS_REG_ENC_BW(sdram_ch.cap_info.bw, 0); + sys_reg |= SYS_REG_ENC_DBW(sdram_ch.cap_info.dbw, 0); writel(sys_reg, &dram->grf->os_reg[2]); @@ -673,7 +673,7 @@ static int sdram_init(struct dram_info *dram, /* release ctrl presetn, and config ctl registers */ rkclk_ddr_reset(dram, 1, 0, 0, 0); pctl_cfg(dram, sdram_params); - sdram_ch.ddrconfig = calculate_ddrconfig(sdram_params); + sdram_ch.cap_info.ddrconfig = calculate_ddrconfig(sdram_params); set_ctl_address_map(dram, sdram_params); phy_cfg(dram, sdram_params); @@ -820,17 +820,17 @@ static u64 dram_detect_cap(struct dram_info *dram, /* restore auto low-power */ writel(pwrctl, pctl_base + DDR_PCTL2_PWRCTL); - sdram_ch.rank = cs + 1; - sdram_ch.col = col; - sdram_ch.bk = bk; - sdram_ch.dbw = dbw; - sdram_ch.bw = bw; - sdram_ch.cs0_row = row; + sdram_ch.cap_info.rank = cs + 1; + sdram_ch.cap_info.col = col; + sdram_ch.cap_info.bk = bk; + sdram_ch.cap_info.dbw = dbw; + sdram_ch.cap_info.bw = bw; + sdram_ch.cap_info.cs0_row = row; if (cs) - sdram_ch.cs1_row = row; + sdram_ch.cap_info.cs1_row = row; else - sdram_ch.cs1_row = 0; - sdram_ch.row_3_4 = row_3_4; + sdram_ch.cap_info.cs1_row = 0; + sdram_ch.cap_info.row_3_4 = row_3_4; if (dram_type == DDR4) cap = 1llu << (cs + row + bk + col + ((dbw == 0) ? 2 : 1) + bw); @@ -856,7 +856,7 @@ static u32 remodify_sdram_params(struct rk3328_sdram_params *sdram_params) tmp &= ~((3ul << 30) | (3ul << 24) | (3ul << 12)); - switch (sdram_ch.dbw) { + switch (sdram_ch.cap_info.dbw) { case 2: tmp |= (3ul << 30); break; @@ -869,16 +869,16 @@ static u32 remodify_sdram_params(struct rk3328_sdram_params *sdram_params) break; } - if (sdram_ch.rank == 2) + if (sdram_ch.cap_info.rank == 2) tmp |= 3 << 24; else tmp |= 1 << 24; - tmp |= (2 - sdram_ch.bw) << 12; + tmp |= (2 - sdram_ch.cap_info.bw) << 12; sdram_params->pctl_regs.pctl[tmp_adr][1] = tmp; - if (sdram_ch.bw == 2) + if (sdram_ch.cap_info.bw == 2) sdram_ch.noc_timings.ddrtiming.b.bwratio = 0; else sdram_ch.noc_timings.ddrtiming.b.bwratio = 1; @@ -893,9 +893,9 @@ static int dram_detect_cs1_row(struct rk3328_sdram_params *sdram_params, u32 cs1_bit; void __iomem *test_addr, *cs1_addr; u32 row, bktmp, coltmp, bw; - u32 ddrconf = sdram_ch.ddrconfig; + u32 ddrconf = sdram_ch.cap_info.ddrconfig; - if (sdram_ch.rank == 2) { + if (sdram_ch.cap_info.rank == 2) { cs1_bit = addrmap[ddrconf][0] + 8; if (cs1_bit > 31) @@ -908,18 +908,18 @@ static int dram_detect_cs1_row(struct rk3328_sdram_params *sdram_params, cs1_bit = 0; if (sdram_params->base.dramtype == DDR4) { - if (sdram_ch.dbw == 0) - bktmp = sdram_ch.bk + 2; + if (sdram_ch.cap_info.dbw == 0) + bktmp = sdram_ch.cap_info.bk + 2; else - bktmp = sdram_ch.bk + 1; + bktmp = sdram_ch.cap_info.bk + 1; } else { - bktmp = sdram_ch.bk; + bktmp = sdram_ch.cap_info.bk; } - bw = sdram_ch.bw; - coltmp = sdram_ch.col; + bw = sdram_ch.cap_info.bw; + coltmp = sdram_ch.cap_info.col; /* detect cs1 row */ - for (row = sdram_ch.cs0_row; row > 12; row--) { + for (row = sdram_ch.cap_info.cs0_row; row > 12; row--) { test_addr = (void __iomem *)(SDRAM_ADDR + cs1_addr + (1ul << (row + cs1_bit + bktmp + coltmp + bw - 1ul))); @@ -954,7 +954,7 @@ static int sdram_init_detect(struct dram_info *dram, sdram_init(dram, sdram_params, 0); /* redetect cs1 row */ - sdram_ch.cs1_row = + sdram_ch.cap_info.cs1_row = dram_detect_cs1_row(sdram_params, 0); return 0;