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Kornilov" X-Patchwork-Id: 1177705 X-Patchwork-Delegate: ykai007@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ptw1AxnH"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 46tRJx4M59z9sP3 for ; Wed, 16 Oct 2019 20:07:45 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 48745C21DB5; Wed, 16 Oct 2019 09:07:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 28FA0C21DD9; Wed, 16 Oct 2019 09:06:48 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id DB62CC21C93; Wed, 16 Oct 2019 09:06:26 +0000 (UTC) Received: from mail-lj1-f193.google.com (mail-lj1-f193.google.com [209.85.208.193]) by lists.denx.de (Postfix) with ESMTPS id 595BDC21D72 for ; Wed, 16 Oct 2019 09:06:23 +0000 (UTC) Received: by mail-lj1-f193.google.com with SMTP id f5so23182216ljg.8 for ; Wed, 16 Oct 2019 02:06:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=crxg0lmG7ghG5RiBZC2W1Fj5kMvsPXqjDvkuppPhIvQ=; b=ptw1AxnHEmW/Onn6RE/Sfn53yCW3KilMxTEtlw3t3fPJCcUUN9Io4617v1VxInfmBI V3o00UL2cSWbxZnLpX83YuaGaT+VBfoLBBzpxi8eMWyzUOjcc5dr5BSf0aERmL3T1k8A m0ZxXQEVZTTZuPFdDfZ6iiWwEf8r2m0HRiU1EzFJcrjL8O1nwnHTt/OfX6EeHc3DNJvE UAkPOa1SDSF/GV7KwcIn9ONiqLx1pig/rWEVyY6mjLLdHHCyPYjXvpRaZjBkFP5fwikf kYaIU+fZ23c8ga7UHm1y2WvbiKA6Eb/FAvyM2+D3Xz8rQan5FKyraaPI9gUva6iBkj0T 9Yyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=crxg0lmG7ghG5RiBZC2W1Fj5kMvsPXqjDvkuppPhIvQ=; b=sk40/dGcZ/LHFivl/LXa1qGZ5yPrGneYdBtmu0pBUNL6V2iYmIFGSVt9kYFRfNvOe2 Xn7gTiiMK1u6Vp10d0Pw48VoxypfOlC5JMD6mVwFBbv18h4iu7WUs39l+q47OfP/5EJ+ FUcJDeKoaqydhXvNPZOYvcHj80fAw05zJWibrF+uIhBcnX3ZeJm4c+yITQZNkOb9GHb9 zENnc/4rndBB7W1n/TtW5F6pSCyMkkzDDUbWVpTt5w+AnBVdCSfWHBHoF2K1nj5e9+EW tuiPMUU0L8ZWLojatiDKxn5HrD3HeXffWb3S98gvbxqzFqoGhW2JAzVyZA1SvoGOYb5/ vJ0A== X-Gm-Message-State: APjAAAUGfGF2TMwAuj50wnsZMS3EnPbeEECARxwv8K6ctNh9KxLoAZAf SzJxIRP3HcljGP7RqhzWmZa7fJBTkpE= X-Google-Smtp-Source: APXvYqxf5/mW/nydguZN1b7TvDmUM/ZchZD3lqHZskAReaTltYDemZMqR+d/8RXp0R8AutoBwG+AnQ== X-Received: by 2002:a2e:9d83:: with SMTP id c3mr25423024ljj.237.1571216781938; Wed, 16 Oct 2019 02:06:21 -0700 (PDT) Received: from alpha.sai.msu.ru ([93.180.21.1]) by smtp.gmail.com with ESMTPSA id c18sm6974258ljd.27.2019.10.16.02.06.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 16 Oct 2019 02:06:21 -0700 (PDT) From: "Matwey V. Kornilov" To: u-boot@lists.denx.de Date: Wed, 16 Oct 2019 12:06:10 +0300 Message-Id: <20191016090612.11356-2-matwey.kornilov@gmail.com> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191016090612.11356-1-matwey.kornilov@gmail.com> References: <20191016090612.11356-1-matwey.kornilov@gmail.com> Cc: Albert Aribaud , "Matwey V. Kornilov" Subject: [U-Boot] [PATCH 1/3] rockchip: rk3328: use common struct sdram_base_params for struct rk3328_sdram_params X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Currently, struct sdram_base_params and struct rk3328_sdram_params have similar layouts. Signed-off-by: Matwey V. Kornilov --- arch/arm/dts/rk3328-sdram-ddr3-666.dtsi | 2 ++ arch/arm/dts/rk3328-sdram-lpddr3-1600.dtsi | 2 ++ arch/arm/dts/rk3328-sdram-lpddr3-666.dtsi | 2 ++ arch/arm/include/asm/arch-rockchip/sdram_rk3328.h | 4 +--- drivers/ram/rockchip/sdram_rk3328.c | 28 +++++++++++------------ 5 files changed, 21 insertions(+), 17 deletions(-) diff --git a/arch/arm/dts/rk3328-sdram-ddr3-666.dtsi b/arch/arm/dts/rk3328-sdram-ddr3-666.dtsi index d99e7e0352..5a26115448 100644 --- a/arch/arm/dts/rk3328-sdram-ddr3-666.dtsi +++ b/arch/arm/dts/rk3328-sdram-ddr3-666.dtsi @@ -26,6 +26,8 @@ 333 3 + 1 + 0 0 0x00000000 diff --git a/arch/arm/dts/rk3328-sdram-lpddr3-1600.dtsi b/arch/arm/dts/rk3328-sdram-lpddr3-1600.dtsi index cc0011cf7b..11c1df9164 100644 --- a/arch/arm/dts/rk3328-sdram-lpddr3-1600.dtsi +++ b/arch/arm/dts/rk3328-sdram-lpddr3-1600.dtsi @@ -27,6 +27,8 @@ 800 6 1 + 0 + 1 0x00000000 0x43041008 diff --git a/arch/arm/dts/rk3328-sdram-lpddr3-666.dtsi b/arch/arm/dts/rk3328-sdram-lpddr3-666.dtsi index 62d809e833..ad3f3e7ee8 100644 --- a/arch/arm/dts/rk3328-sdram-lpddr3-666.dtsi +++ b/arch/arm/dts/rk3328-sdram-lpddr3-666.dtsi @@ -26,6 +26,8 @@ 333 6 + 1 + 0 0 0x00000000 diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h index 11411ead10..ea5f5bfd86 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h @@ -428,9 +428,7 @@ struct rk3328_sdram_channel { struct rk3328_sdram_params { struct rk3328_sdram_channel ch; - unsigned int ddr_freq; - unsigned int dramtype; - unsigned int odt; + struct sdram_base_params base; struct rk3328_ddr_pctl_regs pctl_regs; struct rk3328_ddr_phy_regs phy_regs; struct rk3328_ddr_skew skew; diff --git a/drivers/ram/rockchip/sdram_rk3328.c b/drivers/ram/rockchip/sdram_rk3328.c index 656696ac3c..59b1638785 100644 --- a/drivers/ram/rockchip/sdram_rk3328.c +++ b/drivers/ram/rockchip/sdram_rk3328.c @@ -122,7 +122,7 @@ static void rkclk_configure_ddr(struct dram_info *dram, clrbits_le32(PHY_REG(phy_base, 0xef), 1 << 7); /* for inno ddr phy need 2*freq */ - rkclk_set_dpll(dram, sdram_params->ddr_freq * 2); + rkclk_set_dpll(dram, sdram_params->base.ddr_freq * 2); } static void phy_soft_reset(struct dram_info *dram) @@ -154,7 +154,7 @@ static int pctl_cfg(struct dram_info *dram, * dfi_lp_en_pd=1,dfi_lp_wakeup_pd=2 * hw_lp_idle_x32=1 */ - if (sdram_params->dramtype == LPDDR3) { + if (sdram_params->base.dramtype == LPDDR3) { setbits_le32(pctl_base + DDR_PCTL2_DFILPCFG0, 1); clrsetbits_le32(pctl_base + DDR_PCTL2_DFILPCFG0, 0xf << 4, @@ -230,7 +230,7 @@ static unsigned int calculate_ddrconfig(struct rk3328_sdram_params *sdram_params row = sdram_ch.cs0_row; bank = sdram_ch.bk; - if (sdram_params->dramtype == DDR4) { + if (sdram_params->base.dramtype == DDR4) { tmp = ((cs - 1) << 6) | ((row - 13) << 3) | (bw & 0x2) | die_bw; for (i = 10; i < 17; i++) { if (((tmp & 0x7) == (ddr4_cfg_2_rbc[i - 10] & 0x7)) && @@ -286,9 +286,9 @@ static void set_ctl_address_map(struct dram_info *dram, copy_to_reg((u32 *)(pctl_base + DDR_PCTL2_ADDRMAP0), &addrmap[sdram_ch.ddrconfig][0], 9 * 4); - if (sdram_params->dramtype == LPDDR3 && sdram_ch.row_3_4) + if (sdram_params->base.dramtype == LPDDR3 && sdram_ch.row_3_4) setbits_le32(pctl_base + DDR_PCTL2_ADDRMAP6, 1 << 31); - if (sdram_params->dramtype == DDR4 && sdram_ch.bw == 0x1) + if (sdram_params->base.dramtype == DDR4 && sdram_ch.bw == 0x1) setbits_le32(pctl_base + DDR_PCTL2_PCCFG, 1 << 8); if (sdram_ch.rank == 1) @@ -332,7 +332,7 @@ static void set_ds_odt(struct dram_info *dram, u32 cmd_drv, clk_drv, dqs_drv, dqs_odt; void __iomem *phy_base = dram->phy; - if (sdram_params->dramtype == DDR3) { + if (sdram_params->base.dramtype == DDR3) { cmd_drv = PHY_DDR3_RON_RTT_34ohm; clk_drv = PHY_DDR3_RON_RTT_45ohm; dqs_drv = PHY_DDR3_RON_RTT_34ohm; @@ -373,7 +373,7 @@ static void phy_cfg(struct dram_info *dram, u32 i; void __iomem *phy_base = dram->phy; - phy_dll_bypass_set(dram, sdram_params->ddr_freq); + phy_dll_bypass_set(dram, sdram_params->base.ddr_freq); for (i = 0; sdram_params->phy_regs.phy[i][0] != 0xFFFFFFFF; i++) { writel(sdram_params->phy_regs.phy[i][1], phy_base + sdram_params->phy_regs.phy[i][0]); @@ -587,7 +587,7 @@ static void dram_all_config(struct dram_info *dram, set_ddrconfig(dram, sdram_ch.ddrconfig); - sys_reg |= SYS_REG_ENC_DDRTYPE(sdram_params->dramtype); + sys_reg |= SYS_REG_ENC_DDRTYPE(sdram_params->base.dramtype); sys_reg |= SYS_REG_ENC_ROW_3_4(sdram_ch.row_3_4, 0); sys_reg |= SYS_REG_ENC_RANK(sdram_ch.rank, 0); sys_reg |= SYS_REG_ENC_COL(sdram_ch.col, 0); @@ -653,7 +653,7 @@ static int sdram_init(struct dram_info *dram, rkclk_ddr_reset(dram, 1, 1, 1, 0); rkclk_configure_ddr(dram, sdram_params); if (pre_init == 0) { - switch (sdram_params->dramtype) { + switch (sdram_params->base.dramtype) { case DDR3: printf("DDR3\n"); break; @@ -685,13 +685,13 @@ static int sdram_init(struct dram_info *dram, continue; /* do ddr gate training */ - if (data_training(dram, 0, sdram_params->dramtype) != 0) { + if (data_training(dram, 0, sdram_params->base.dramtype) != 0) { printf("data training error\n"); return -1; } - if (sdram_params->dramtype == DDR4) - write_vrefdq(dram, 0x3, 5670, sdram_params->dramtype); + if (sdram_params->base.dramtype == DDR4) + write_vrefdq(dram, 0x3, 5670, sdram_params->base.dramtype); if (pre_init == 0) { rx_deskew_switch_adjust(dram); @@ -724,7 +724,7 @@ static u64 dram_detect_cap(struct dram_info *dram, u32 cs; u32 bw = 1; u64 cap = 0; - u32 dram_type = sdram_params->dramtype; + u32 dram_type = sdram_params->base.dramtype; u32 pwrctl; if (dram_type != DDR4) { @@ -907,7 +907,7 @@ static int dram_detect_cs1_row(struct rk3328_sdram_params *sdram_params, else cs1_bit = 0; - if (sdram_params->dramtype == DDR4) { + if (sdram_params->base.dramtype == DDR4) { if (sdram_ch.dbw == 0) bktmp = sdram_ch.bk + 2; else