From patchwork Tue Oct 15 20:10:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Goldschmidt X-Patchwork-Id: 1177381 X-Patchwork-Delegate: simon.k.r.goldschmidt@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Ezv+zAq7"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 46t6G333NKz9sPZ for ; Wed, 16 Oct 2019 07:19:07 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 1EF62C21C93; Tue, 15 Oct 2019 20:12:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 5CCD5C21DE8; Tue, 15 Oct 2019 20:11:06 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 5D9ABC21C50; Tue, 15 Oct 2019 20:10:48 +0000 (UTC) Received: from mail-wr1-f65.google.com (mail-wr1-f65.google.com [209.85.221.65]) by lists.denx.de (Postfix) with ESMTPS id A68A1C21D74 for ; Tue, 15 Oct 2019 20:10:45 +0000 (UTC) Received: by mail-wr1-f65.google.com with SMTP id z9so25347706wrl.11 for ; Tue, 15 Oct 2019 13:10:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EGTEANj3OXg08KKRq5P+8CtEBrsZm06eouSce4wEZFk=; b=Ezv+zAq78YTC/lSBWVBZdaj18b98CvBGzmAteX6VSZrkorT9a5P6wfN+iAiX+H/QTA C3H2NxFy6Jl5ur1fOk/6wbT4ZzpgbfdalEFE4eaNvRvlaYNKkb5v3nwqKLYJqlOSIGk1 7Ly9bTUjHNARi9RiPDn0FhOnCBg+SkvqcEDOVa+0PHPC3K6z4NbosDiWYkqMsWhjOj3X QNsiR0M67fUkLd3oLIPyKR6/BbXWj1z7g6PYqu02jetE+ZXpm7UL7LSzhO5NmW/FI4b9 Tdt3FhhLwFJtF/KB2tBFwac2U95PNteme6XH56q8UO8+ePnCuV/JvckgyaOniHlDyRCC dq+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EGTEANj3OXg08KKRq5P+8CtEBrsZm06eouSce4wEZFk=; b=YaaGDASIVoc4E7mV/Eagu5to4d0D8y55RsmmbwuGliEc4qgakysmBX2+FsqD1rGEMj 1Y2WUMKYBkaTdhsYB7nnSEJhLMu/7qD8Agi9Zy9Q55xePqp1IjuwS3u51a6S9PhhYfjs 4cU1BM9fsEPv5oVD5cYLAMxfRHFeSuCsDd5sae0zcIADuECK9lgQnjykQ8slGGrDbdMY Z3FxMUXchEJewfcL+WBXmUaI+hBujHaThB9PT6F6eyrXbTLNuiGhVA5DA4Tv1mAKvoN9 3GTCDxI+dVoa9GFZ70At4esZJxhR7wEfSW1qWTNM/LbfY6gHbf8WMMHIWiWFJHxwMbGH 3gSw== X-Gm-Message-State: APjAAAXZodsO7l2kxHsR2H71+7LvCcKgQpj2BIqQV4NFOKIJ4i/fBaGb cQvFncZHhoG7D3FuMB1Axk4tvRCe X-Google-Smtp-Source: APXvYqy7JOnWaVpM9P94AwYcITllpU+Z2RFDVMB/RMdfeG8IPjikLzAo7Ide8SZZXpZwg39lQ8/OWw== X-Received: by 2002:adf:e98d:: with SMTP id h13mr30747201wrm.70.1571170245261; Tue, 15 Oct 2019 13:10:45 -0700 (PDT) Received: from ubuntu.home ([2a02:8071:6a3:700:9d84:c831:fe55:4622]) by smtp.gmail.com with ESMTPSA id 79sm329194wmb.7.2019.10.15.13.10.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2019 13:10:44 -0700 (PDT) From: Simon Goldschmidt To: Dalon L Westergreen Date: Tue, 15 Oct 2019 22:10:18 +0200 Message-Id: <20191015201032.20156-6-simon.k.r.goldschmidt@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191015201032.20156-1-simon.k.r.goldschmidt@gmail.com> References: <20191015201032.20156-1-simon.k.r.goldschmidt@gmail.com> MIME-Version: 1.0 Cc: Marek Vasut , Albert Aribaud , u-boot@lists.denx.de, Joe Hershberger , Tom Rini Subject: [U-Boot] [RFC PATCH v2 05/18] arm: socfpga: gen5: move initial reset handling to reset driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This moves disabling all peripherals from ad-hoc code in arch/arm to the socfpga reset driver. To do this, DM initialization and UCLASS_RESET probing has to be done earlier in the SPL. Also, the gen5 devicetrees need an added property that tells the reset driver which bits to set and which need to be left at 0 (L4WD0). Signed-off-by: Simon Goldschmidt --- Changes in v2: - add dts based reset handling (messed up in v1) arch/arm/dts/socfpga-common-u-boot.dtsi | 1 + arch/arm/mach-socfpga/reset_manager_gen5.c | 13 -------- arch/arm/mach-socfpga/spl_gen5.c | 21 ++++++------ drivers/reset/reset-socfpga.c | 37 ++++++++++++++++++++-- 4 files changed, 45 insertions(+), 27 deletions(-) diff --git a/arch/arm/dts/socfpga-common-u-boot.dtsi b/arch/arm/dts/socfpga-common-u-boot.dtsi index 322c858c4b..aebe476e3f 100644 --- a/arch/arm/dts/socfpga-common-u-boot.dtsi +++ b/arch/arm/dts/socfpga-common-u-boot.dtsi @@ -12,6 +12,7 @@ &rst { u-boot,dm-pre-reloc; + altr,modrst-reset-val = <1 0xffffffbf 0xffffffff>; }; &sdr { diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c b/arch/arm/mach-socfpga/reset_manager_gen5.c index 9a32f5abfe..34e59b852b 100644 --- a/arch/arm/mach-socfpga/reset_manager_gen5.c +++ b/arch/arm/mach-socfpga/reset_manager_gen5.c @@ -48,19 +48,6 @@ void socfpga_per_reset(u32 reset, int set) clrbits_le32(reg, 1 << RSTMGR_RESET(reset)); } -/* - * Assert reset on every peripheral but L4WD0. - * Watchdog must be kept intact to prevent glitches - * and/or hangs. - */ -void socfpga_per_reset_all(void) -{ - const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)); - - writel(~l4wd0, &reset_manager_base->per_mod_reset); - writel(0xffffffff, &reset_manager_base->per2_mod_reset); -} - #define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10 #define L3REGS_REMAP_HPS2FPGA_MASK 0x08 #define L3REGS_REMAP_OCRAM_MASK 0x01 diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index 87b76b47de..1ae8025746 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -84,12 +84,19 @@ void board_init_f(ulong dummy) socfpga_sdram_remap_zero(); socfpga_pl310_clear(); + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + debug("Freezing all I/O banks\n"); /* freeze all IO banks */ sys_mgr_frzctrl_freeze_req(); - /* Put everything into reset but L4WD0. */ - socfpga_per_reset_all(); + ret = uclass_get_device(UCLASS_RESET, 0, &dev); + if (ret) + debug("Reset init failed: %d\n", ret); if (!socfpga_is_booting_from_fpga()) { /* Put FPGA bridges into reset too. */ @@ -130,16 +137,6 @@ void board_init_f(ulong dummy) debug_uart_init(); #endif - ret = spl_early_init(); - if (ret) { - debug("spl_early_init() failed: %d\n", ret); - hang(); - } - - ret = uclass_get_device(UCLASS_RESET, 0, &dev); - if (ret) - debug("Reset init failed: %d\n", ret); - /* enable console uart printing */ preloader_console_init(); diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c index 93ec9cfdb6..c5fd0679c7 100644 --- a/drivers/reset/reset-socfpga.c +++ b/drivers/reset/reset-socfpga.c @@ -106,6 +106,39 @@ static const struct reset_ops socfpga_reset_ops = { .rst_deassert = socfpga_reset_deassert, }; +/* + * This function ensures that in SPL, all peripherals are reset at startup. + * It does this by reading reset values from the device tree. + */ +static int socfpga_reset_set_inital_reset_values(struct udevice *dev) +{ +#ifdef CONFIG_SPL_BUILD + struct socfpga_reset_data *data = dev_get_priv(dev); + int ret; + u32 modrst_vals[5]; + size_t i, sz, offset; + + ret = dev_read_size(dev, "altr,modrst-reset-val"); + if (ret >= sizeof(u32)) { + sz = min(ret/sizeof(u32), ARRAY_SIZE(modrst_vals)); + ret = dev_read_u32_array(dev, "altr,modrst-reset-val", + modrst_vals, sz); + if (ret) { + dev_warn(dev, "Failed to read modrst reset values\n"); + return ret; + } + /* first item is register offset to start */ + offset = modrst_vals[0] * 4; + for (i = 1; i < sz; i++) { + writel(modrst_vals[i], data->modrst_base + offset); + offset += 4; + } + } +#endif + + return 0; +} + static int socfpga_reset_probe(struct udevice *dev) { struct socfpga_reset_data *data = dev_get_priv(dev); @@ -117,7 +150,7 @@ static int socfpga_reset_probe(struct udevice *dev) modrst_offset = dev_read_u32_default(dev, "altr,modrst-offset", 0x10); data->modrst_base = membase + modrst_offset; - return 0; + return socfpga_reset_set_inital_reset_values(dev); } static int socfpga_reset_remove(struct udevice *dev) @@ -163,5 +196,5 @@ U_BOOT_DRIVER(socfpga_reset) = { .priv_auto_alloc_size = sizeof(struct socfpga_reset_data), .ops = &socfpga_reset_ops, .remove = socfpga_reset_remove, - .flags = DM_FLAG_OS_PREPARE, + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_OS_PREPARE, };