diff --git a/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi
index 0a4d54e304..36ae10ab28 100644
--- a/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi
@@ -7,6 +7,7 @@
  */
 
 #include "socfpga-common-u-boot.dtsi"
+#include "socfpga_cyclone5_socrates_handoff.dtsi"
 
 /{
 	aliases {
diff --git a/arch/arm/dts/socfpga_cyclone5_socrates_handoff.dtsi b/arch/arm/dts/socfpga_cyclone5_socrates_handoff.dtsi
new file mode 100644
index 0000000000..4e750796be
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_socrates_handoff.dtsi
@@ -0,0 +1,290 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ *<auto-generated>
+ *	This code was generated by a tool based on
+ *	handoffs from both Qsys and Quartus.
+ *
+ *	Changes to this file may be lost if
+ *	the code is regenerated.
+ *</auto-generated>
+ */
+
+&osc1 {
+	clock-frequency = <25000000>;
+};
+
+&osc2 {
+	clock-frequency = <25000000>;
+};
+
+&f2s_periph_ref_clk {
+	clock-frequency = <0>;
+};
+
+&f2s_sdram_ref_clk {
+	clock-frequency = <0>;
+};
+
+&clkmgr {
+	altr,clk-mgr-cfg = <0xf8010000 0x00000000 0x00000000 0x00000000
+			    0x03000000 0xff010000 0x0f000000 0x95000000
+			    0x04000000 0x00000000 0x03000000 0x38010000
+			    0xff010000 0x03000000 0xff010000 0x04000000
+			    0x04000000 0xff010000 0x40080000 0x69180000
+			    0x1a000000 0x78020200 0x01000000 0x00000000
+			    0x01080000 0x05000000 0x01000000>;
+};
+
+&scanmgr {
+	altr,pinmux-cfg = [00 02 02 02 02 02 02 02
+			   02 00 02 02 02 02 00 00
+			   00 00 00 00 03 00 03 03
+			   00 00 00 00 00 03 03 03
+			   00 01 01 01 01 00 00 01
+			   01 03 03 03 03 02 02 01
+			   01 01 01 00 00 00 00 00
+			   00 00 00 00 00 00 00 00
+			   02 02 02 02 02 02 02 02
+			   02 02 02 02 02 02 00 03
+			   03 03 03 03 03 00 00 00
+			   00 00 00 00 00 00 00 00
+			   00 00 00 00 00 00 00 00
+			   00 00 00 00 00 00 00 00
+			   00 00 00 00 00 01 01 01
+			   01 01 01 01 01 01 01 01
+			   01 01 01 01 01 01 01 01
+			   01 01 01 01 01 01 01 01
+			   01 01 01 01 01 01 01 01
+			   01 01 01 01 01 01 01 01
+			   01 01 01 01 01 01 01 01
+			   01 01 01 01 01 01 01 01
+			   01 01 01 01 01 01 01 01
+			   01 01 01 01 00 00 00 00
+			   00 00 00 00 00 00 00 00
+			   00 00 00 00 00 00 00];
+	altr,iocsr-scan-chain0-table = <0x00000000 0x00000000 0x0000f00f 0x000000c0
+					0x3f000000 0x00800000 0x24480000 0x00902001
+					0x00004082 0x04800100 0x00000000 0x00400000
+					0x12240000 0x00489000 0x00002041 0x02000080
+					0x04090000 0x00200000 0x09120000 0x00244800
+					0x00009020 0x01000040 0x82040000 0x00100000>;
+	altr,iocsr-scan-chain1-table = <0x48900000 0x00204102 0xc0008004 0x09000000
+					0x12240000 0x00800000 0x24480000 0x00902001
+					0x00004082 0x04000000 0x09120000 0x00400000
+					0x12240000 0x00489000 0x00002041 0x02000080
+					0x04090000 0x00200000 0x09120006 0x00244800
+					0x0000fe01 0x000000f8 0x07000000 0x00100080
+					0x04090000 0x00122400 0x00004890 0x00300020
+					0x41020000 0x00080000 0x00000000 0x00000000
+					0x00002448 0x00000090 0x20010000 0x00040000
+					0x00000000 0x80040900 0x03000000 0x00000000
+					0x00000000 0x00020090 0x20016000 0x00000000
+					0x00000912 0x00060024 0x48000000 0x00010048
+					0x90003000 0x204102c0 0x00800409 0x00030012
+					0x24000c00 0x80000000>;
+	altr,iocsr-scan-chain2-table = <0x48900030 0x00000000 0x0000f00f 0x00000000
+					0x1224000c 0x00800000 0x24480018 0x00000000
+					0x00004082 0x04800100 0x09120006 0x00400000
+					0x12240420 0x00489000 0x30000000 0x00000080
+					0x04090003 0x00200000 0x09120010 0x00244800
+					0x00009020 0x01000140 0x82040000 0x00100080
+					0x04090000 0x00000000 0x00004890 0x00800020
+					0x4102c000 0x00080000>;
+	altr,iocsr-scan-chain3-table = <0x800dc20c 0xff00300c 0x0140800a 0x00009007
+					0x00000208 0x00001000 0x0000800a 0x00009007
+					0x00000208 0x00001000 0x00004320 0x0130000c
+					0x8104c000 0x00000000 0x21000000 0x04000082
+					0x00004005 0x0000c803 0x00000104 0x00000800
+					0x00004005 0x0000c803 0x00004005 0x0000c803
+					0x00802190 0x00180086 0x40026000 0x18020980
+					0x01000000 0x02000040 0x0000a002 0x0000e401
+					0x0000a002 0x0000e401 0x0000a002 0x0000e401
+					0x0000a002 0x0000e401 0x00c01048 0x000c0043
+					0x20013000 0x0c8104c0 0x00300412 0x00030020
+					0x00000400 0x00006750 0x10000000 0x00005924
+					0x00100000 0x340000a0 0x0100000d 0x280a68c0
+					0x30400345 0x011a4812 0xd080a280 0x060c0334
+					0x5014a001 0x00000d28 0x0a68c030 0x40034902
+					0x1a0000d0 0x80a28006 0x00000410 0x00002000
+					0x00000410 0x00002000 0x00000015 0x0000200f
+					0x00000015 0x0000200f 0x0000fe01 0x00000018
+					0x02098001 0x60082400 0x06807f00 0x00000000
+					0x0100800a 0x00009007 0x0000800a 0x00009007
+					0x0000800a 0x00009007 0x00000208 0x00001000
+					0x00004320 0x0130000c 0x8104c000 0xf00f0000
+					0x00c01048 0x000c0080 0x00004005 0x00004802
+					0x00000004 0x00000800 0x00004005 0x0000c803
+					0x00004005 0x0000c803 0x00802190 0x00180086
+					0x40026000 0x18020980 0x01600824 0x00060040
+					0x4000a002 0x0000e401 0x0000a002 0x0000e401
+					0x0000a002 0x0000e401 0x0000a002 0x0000e401
+					0x00c01048 0x000c0043 0x20013000 0x0c8104c0
+					0x00300412 0x00030020 0x00000400 0x00006750
+					0x10000000 0x00005924 0x00100000 0x340000a0
+					0x0100000d 0x280a68c0 0x30400349 0x021a4812
+					0xd080a280 0x060c0334 0x4000a001 0x02000d28
+					0x0a68c030 0x40034902 0x1a280ad0 0x80a28006
+					0x00000410 0x00002000 0x00000410 0x00002000
+					0x00000015 0x0000200f 0x00000015 0x0000200f
+					0x0000fe01 0x00000018 0x02098001 0x60082400
+					0x06807f00 0x00000000 0x01003099 0x00343434
+					0x00400daa 0x00a8c301 0x00400daa 0x00a8c301
+					0x00400daa 0x00a8c301 0x00010400 0x00080000
+					0x00000000 0x08120000 0x00204800 0x00000001
+					0x00000000 0x82044100 0x00a00600 0x00b40100
+					0x00000200 0x00040000 0x00a00200 0x00e40100
+					0x00a00655 0x00d4e100 0x00000000 0x0c094320
+					0x01300000 0x00004090 0x00000000 0x43c22020
+					0x0050832a 0x00ea7000 0x0050832a 0x00ea7000
+					0x0050832a 0x00ea7000 0x40000100 0x00020000
+					0x00000000 0x82040000 0x00081200 0x00200000
+					0x00000080 0x20411000 0x00020000 0x805f0dac
+					0xffffffff 0x0d69f314 0x1414041a 0x0000d000
+					0x00408618 0x067a2449 0xd5a328f2 0x1e45d1f6
+					0x88e34203 0x00001a82 0x00d00000 0x80061405
+					0x7a2449d9 0xa328f21e 0x45d1f688 0xe3520300
+					0x00020800 0x00100000 0x00020800 0x00100000
+					0x00800a00 0x00500700 0x00801a54 0x01508703
+					0x00000010 0x00000000 0x00c08000 0x00000041
+					0xc23f0000 0x00008200 0x00400daa 0x00a8c301
+					0x00400daa 0x00a8c301 0x00400daa 0x00a8c301
+					0x00010400 0x00080000 0x00000000 0x08120000
+					0x00204800 0x00800000 0x00000000 0x82044100
+					0x00a00600 0x00b40100 0x00000200 0x00040000
+					0x80000200 0x00040000 0x00a00655 0x00d4e100
+					0x00000000 0x0c090000 0x10000000 0x00004090
+					0x00000000 0x43c22020 0x0050832a 0x00ea7000
+					0x0050832a 0x00ea7000 0x0050832a 0x00ea7000
+					0x00500100 0x00f20000 0x00000000 0x82040000
+					0x00081286 0x40026000 0x00000080 0x20411000
+					0x00020000 0x805f0dac 0xffffffff 0x0d69f314
+					0x1414041a 0x0000d000 0x00408618 0x067a2449
+					0xd523cff3 0x1e45d1f4 0x48924a03 0x8e031a82
+					0x00d00000 0x80060000 0x7a2449d9 0x23cff31e
+					0x45d1f488 0xe3520300 0x00020800 0x00100000
+					0x00020800 0x00100000 0x00800a00 0x00500700
+					0x00801a54 0x01508703 0x00000010 0x00000000
+					0x00c08000 0x00000041 0x02000004 0x00008200
+					0x00400daa 0x00a8c301 0x00400daa 0x00a8c301
+					0x00400daa 0x00a8c301 0x00010400 0x00080000
+					0x00000000 0x08120000 0x00204800 0x00800000
+					0x00000000 0x82044100 0x00a00600 0x00b40100
+					0x00000200 0x00040000 0x00a00200 0x00e40100
+					0x00a00655 0x00d4e100 0x00000000 0x0c094320
+					0x01300000 0x00004090 0x00000000 0x43c22020
+					0x0050832a 0x00ea7000 0x0050832a 0x00ea7000
+					0x0050832a 0x00ea7000 0x40000100 0x00020000
+					0x00000000 0x82040000 0x00081200 0x00200000
+					0x00000080 0x20411000 0x00020000 0x805f0dac
+					0xffffffff 0x0d69f314 0x1414041a 0x0000d000
+					0x00408618 0x067a2449 0xd9a328f2 0x1e45d1f4
+					0x48924a03 0x00001a82 0x00d00000 0x80060000
+					0x7a2449d9 0xa328f21e 0x45d1f488 0xe3520300
+					0x00020800 0x00100000 0x00020800 0x00100000
+					0x00800a00 0x00500700 0x00801a54 0x01508703
+					0x00000010 0x00000000 0x00c08000 0x00000041
+					0x02000004 0x00008200 0x00400daa 0x00a8c301
+					0x00400daa 0x00a8c301 0x00400daa 0x00a8c301
+					0x00010400 0x00080000 0x00000000 0x08120000
+					0x00204800 0x00800000 0x00000000 0x82044100
+					0x00a00600 0x00b40100 0x00000200 0x00040000
+					0x80000200 0x00040000 0x00a00655 0x00d4e100
+					0x00000000 0x0c090000 0x10000000 0x00004090
+					0x00000000 0x43c22020 0x0050832a 0x00ea7000
+					0x0050832a 0x00ea7000 0x0050832a 0x00ea7000
+					0x40000100 0x00020000 0x00000000 0x82040000
+					0x00081200 0x00004000 0x00000080 0x20411000
+					0x00020000 0x805f0dac 0xffffffff 0x0d69f114
+					0x1414041a 0x0000d000 0x00408608 0x027a2449
+					0xd923cff3 0x1e45d1f4 0x88e34203 0x00001a82
+					0x00d00000 0x80060000 0x7a2449d9 0x23cff31e
+					0x79def488 0xa2420300 0x00020800 0x00100000
+					0x00020800 0x00100000 0x00800a00 0x00500700
+					0x00801a54 0x01508703 0x00000010 0x00000000
+					0x00c08000 0x00000041 0x02000004 0x00008200
+					0x00984800 0x1a1a1a80 0x00020000 0x04000080
+					0x00020000 0x04000080 0x00020000 0x04000080
+					0x00020000 0x04000000 0x00000400 0x00000010
+					0x00000000 0x40000000 0x00000100 0x00200040
+					0x00010000 0x02000040 0x00010000 0x02000040
+					0x00010000 0x02000040 0x00010000 0x02000000
+					0x00000200 0x00000008 0x00000000 0x20000000
+					0x00800000 0x00100020 0x80000000 0x01000020
+					0x80000000 0x01000020 0x80000000 0x01000020
+					0x80000000 0x01000000 0x00000100 0x00000004
+					0x0000ff00 0x00000000 0x00400000 0x00080000
+					0x010000c0 0x19140400 0x00000040 0x16080004
+					0x00000d00 0x00680000 0x40030000 0x1a0000d0
+					0x00008006 0x00003400 0x00a00100 0x000d0000
+					0x68000040 0x0300001a 0x0000d000 0x00800600
+					0x00340000 0xa0010000 0x01040000 0x08000000
+					0x01040000 0x08000000 0x01040000 0x08000000
+					0x01040000 0x08000080 0x7f000000 0x00000020
+					0x00000000 0x800000e0 0x1f000000 0x00400000>;
+};
+
+&sdr {
+	altr,sdr-cfg = <0x42800a00 0x060c3975 0x14a5aa08 0xc4222200
+			0x000e0000 0x00000800 0x01000000 0x00000000
+			0xea0d0000 0x20000000 0x08000000 0x00000000
+			0x30000000 0x02000000 0x02000000 0x55450400
+			0x0010012c 0x8800b000 0x10027600 0x43059800
+			0x6aa50500 0x00000000 0x00000000 0x00000000
+			0x8810fd3f 0x10420821 0x84ef8180 0x00000000
+			0x00f80000 0x20088220 0x08822008 0x41100441
+			0x10044100 0x01010101 0x01010101 0x01010000
+			0x00020000>;
+	altr,sdr-rw-mgr-cfg = [0d 0e 10 0f 49 4c 54 18
+			       1b 1f 19 1d 00 7b 7a 6f
+			       74 22 25 24 23 32 21 36
+			       39 38 37 46 35 02 08 07
+			       0c 03 09 04 0a 05 0b 12
+			       59 61 6b 14 01 7d 06 04
+			       00 04 20 08 08 04 04 01
+			       01 01 01];
+	altr,sdr-io-cfg = [77 00 19 19 08 00 1f 00
+			   07 1f 04 04 1f 1f 00 00];
+	altr,sdr-misc-cfg = [8d 04 55 55 01 07 05 00
+			     05 10 52 20 20 52 63 0a];
+	altr,sdr-ac-rom-init = <0x00007020 0x00007820 0x21020810 0x20030810
+				0x44000910 0x08000a10 0x00000b10 0x00043810
+				0x41020810 0xc0020810 0x24000a10 0x10000910
+				0x00000b10 0x00007830 0x00007838 0x00007830
+				0x00006810 0x00006b10 0x00042810 0x00004810
+				0x0000981c 0x00009b1c 0x0800981c 0x08009b1c
+				0x0000f838 0x0000f83c 0x00007838 0x00001818
+				0x00009818 0x00005813 0x00005b13 0x08005813
+				0x08005b13 0x00007833 0x08005810 0x00007810>;
+	altr,sdr-inst-rom-init = <0x00000800 0x80060800 0x80810000 0x00820000
+				  0x80820000 0x00830000 0x80830000 0x00810000
+				  0x80840000 0x00850000 0x80850000 0x00860000
+				  0x00840000 0x00080000 0x80860000 0x80080000
+				  0x80a60000 0x80060800 0x00090000 0x80060800
+				  0x80090000 0x80a60000 0x80860000 0x80060800
+				  0x680b0000 0xe8cc0000 0xe80a0000 0xe88c0000
+				  0x880b0000 0x88ec0000 0x080a0000 0x88ac0000
+				  0x80060800 0x00ce0000 0x80cd0000 0x00e70000
+				  0x000c0000 0xe00c0200 0xe00c0200 0xe00c0200
+				  0xe00c0200 0x000d0000 0x80060000 0x80060000
+				  0x80060000 0x80060000 0x800e0600 0x80100600
+				  0x80100600 0x80100600 0x80a60000 0x80860000
+				  0x80060800 0x00ce0000 0x80cd0000 0x00e70000
+				  0x000c0000 0xe00c0300 0xe00c0300 0xe00c0300
+				  0xe00c0300 0x000d0000 0x80060000 0x80060000
+				  0x80060000 0x80060000 0x800e0700 0x80100700
+				  0x80100700 0x80100700 0x80a60000 0x80860000
+				  0x80060800 0x58110000 0xd8060000 0x80060800
+				  0x68110000 0xe8070000 0xe8070000 0xe8870000
+				  0xe80f0400 0xe8100400 0xe8100400 0xe8100400
+				  0x68110000 0xe8070000 0xe8070000 0xe8a70000
+				  0x80060800 0x880e0400 0x88100400 0x88100400
+				  0x88100400 0x680f0400 0xe8100400 0xe8100400
+				  0xe8100400 0x80a60000 0xe80f0400 0xe8100400
+				  0xe8100400 0xe8100400 0x08100400 0x88100400
+				  0x88100400 0x88100400 0x00110000 0x80c60000
+				  0x80860000 0x80e60000 0x80060800 0x00000000
+				  0x00800000 0x00a00000 0x00c00000 0x00000800
+				  0x80000000 0x80800000 0x80a00000 0x80c00000
+				  0x80000800 0x80910000 0x80860000 0x80a60000
+				  0x80060800 0x080f0400 0x80060800>;
+};
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 4b77990f74..c6281373f7 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -15,7 +15,6 @@ obj-y	+= reset_manager_gen5.o
 obj-y	+= scan_manager.o
 obj-y	+= system_manager_gen5.o
 obj-y	+= timer.o
-obj-y	+= wrap_pll_config.o
 obj-y	+= fpga_manager.o
 endif
 
@@ -44,7 +43,6 @@ obj-y	+= spl_gen5.o
 obj-y	+= freeze_controller.o
 obj-y	+= wrap_iocsr_config.o
 obj-y	+= wrap_pinmux_config.o
-obj-y	+= wrap_sdram_config.o
 endif
 ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
 obj-y	+= spl_a10.o
@@ -58,6 +56,4 @@ ifdef CONFIG_TARGET_SOCFPGA_GEN5
 # QTS-generated config file wrappers
 CFLAGS_wrap_iocsr_config.o	+= -I$(srctree)/board/$(BOARDDIR)
 CFLAGS_wrap_pinmux_config.o	+= -I$(srctree)/board/$(BOARDDIR)
-CFLAGS_wrap_pll_config.o	+= -I$(srctree)/board/$(BOARDDIR)
-CFLAGS_wrap_sdram_config.o	+= -I$(srctree)/board/$(BOARDDIR)
 endif
diff --git a/arch/arm/mach-socfpga/freeze_controller.c b/arch/arm/mach-socfpga/freeze_controller.c
index d48aeec374..3ed6229631 100644
--- a/arch/arm/mach-socfpga/freeze_controller.c
+++ b/arch/arm/mach-socfpga/freeze_controller.c
@@ -109,7 +109,6 @@ void sys_mgr_frzctrl_thaw_req(void)
 	u32 reg_cfg_mask;
 	u32 reg_value;
 	u32 channel_id;
-	unsigned long eosc1_freq;
 
 	/* select software FSM */
 	writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW,	&freeze_controller_base->src);
@@ -160,9 +159,12 @@ void sys_mgr_frzctrl_thaw_req(void)
 	setbits_le32(&freeze_controller_base->hioctrl,
 		SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK);
 
-	/* Delay 1000 intosc cycles. The intosc is based on eosc1. */
-	eosc1_freq = cm_get_osc_clk_hz(1) / 1000;	/* kHz */
-	udelay(DIV_ROUND_UP(1000000, eosc1_freq));
+	/*
+	 * Delay 1000 intosc cycles. The intosc is based on eosc1.
+	 * Use worst case which is fatest eosc1=50MHz, delay required
+	 * is 1/50MHz * 1000 = 20us
+	 */
+	udelay(20);
 
 	/*
 	 * de-assert active low bhniotri signals,
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
index a9efe2a377..3b52986f78 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
@@ -111,8 +111,6 @@ struct socfpga_clock_manager {
 	u32	_pad_0xe8_0x200[70];
 };
 
-/* Clock configuration accessors */
-const struct cm_config * const cm_get_default_config(void);
 #endif /* __ASSEMBLER__ */
 
 #define LOCKED_MASK \
diff --git a/arch/arm/mach-socfpga/include/mach/sdram_gen5.h b/arch/arm/mach-socfpga/include/mach/sdram_gen5.h
index 7353b1c5e6..47b5793271 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram_gen5.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram_gen5.h
@@ -7,14 +7,6 @@
 
 #ifndef __ASSEMBLY__
 
-const struct socfpga_sdram_config *socfpga_get_sdram_config(void);
-
-void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem);
-void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem);
-const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void);
-const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void);
-const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void);
-
 #define SDR_CTRLGRP_ADDRESS	(SOCFPGA_SDR_ADDRESS | 0x5000)
 
 struct socfpga_sdr_ctrl {
diff --git a/arch/arm/mach-socfpga/wrap_pll_config.c b/arch/arm/mach-socfpga/wrap_pll_config.c
deleted file mode 100644
index bd631e0fb5..0000000000
--- a/arch/arm/mach-socfpga/wrap_pll_config.c
+++ /dev/null
@@ -1,146 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2015 Marek Vasut <marex@denx.de>
- */
-
-#include <common.h>
-#include <asm/arch/clock_manager.h>
-#include <qts/pll_config.h>
-
-#define MAIN_VCO_BASE (					\
-	(CONFIG_HPS_MAINPLLGRP_VCO_DENOM <<		\
-		CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) |	\
-	(CONFIG_HPS_MAINPLLGRP_VCO_NUMER <<		\
-		CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET)	\
-	)
-
-#define PERI_VCO_BASE (					\
-	(CONFIG_HPS_PERPLLGRP_VCO_PSRC <<		\
-		CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) |	\
-	(CONFIG_HPS_PERPLLGRP_VCO_DENOM <<		\
-		CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) |	\
-	(CONFIG_HPS_PERPLLGRP_VCO_NUMER <<		\
-		CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET)	\
-	)
-
-#define SDR_VCO_BASE (					\
-	(CONFIG_HPS_SDRPLLGRP_VCO_SSRC <<		\
-		CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) |	\
-	(CONFIG_HPS_SDRPLLGRP_VCO_DENOM <<		\
-		CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) |	\
-	(CONFIG_HPS_SDRPLLGRP_VCO_NUMER <<		\
-		CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET)	\
-	)
-
-static const struct cm_config cm_default_cfg = {
-	/* main group */
-	MAIN_VCO_BASE,
-	(CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT <<
-		CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET),
-	(CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT <<
-		CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET),
-	(CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT <<
-		CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET),
-	(CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT <<
-		CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET),
-	(CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT <<
-		CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
-	(CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<
-		CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET),
-	(CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK <<
-		CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) |
-	(CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<
-		CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) |
-	(CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK <<
-		CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) |
-	(CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<
-		CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET),
-	(CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK <<
-		CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) |
-	(CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK <<
-		CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET),
-	(CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<
-		CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET),
-	(CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP <<
-		CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) |
-	(CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP <<
-		CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET),
-
-	/* peripheral group */
-	PERI_VCO_BASE,
-	(CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT <<
-		CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET),
-	(CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT <<
-		CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET),
-	(CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT <<
-		CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET),
-	(CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT <<
-		CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
-	(CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT <<
-		CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET),
-	(CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<
-		CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET),
-	(CONFIG_HPS_PERPLLGRP_DIV_USBCLK <<
-		CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) |
-	(CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK <<
-		CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) |
-	(CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK <<
-		CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) |
-	(CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK <<
-		CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET),
-	(CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<
-		CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET),
-	(CONFIG_HPS_PERPLLGRP_SRC_QSPI <<
-		CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) |
-	(CONFIG_HPS_PERPLLGRP_SRC_NAND <<
-		CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) |
-	(CONFIG_HPS_PERPLLGRP_SRC_SDMMC <<
-		CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET),
-
-	/* sdram pll group */
-	SDR_VCO_BASE,
-	(CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<
-		CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) |
-	(CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT <<
-		CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET),
-	(CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE <<
-		CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) |
-	(CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<
-		CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET),
-	(CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE <<
-		CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) |
-	(CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT <<
-		CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET),
-	(CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<
-		CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) |
-	(CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
-		CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
-
-	/* altera group */
-	CONFIG_HPS_ALTERAGRP_MPUCLK,
-};
-
-const struct cm_config * const cm_get_default_config(void)
-{
-	return &cm_default_cfg;
-}
-
-const unsigned int cm_get_osc_clk_hz(const int osc)
-{
-	if (osc == 1)
-		return CONFIG_HPS_CLK_OSC1_HZ;
-	else if (osc == 2)
-		return CONFIG_HPS_CLK_OSC2_HZ;
-	else
-		return 0;
-}
-
-const unsigned int cm_get_f2s_per_ref_clk_hz(void)
-{
-	return CONFIG_HPS_CLK_F2S_PER_REF_HZ;
-}
-
-const unsigned int cm_get_f2s_sdr_ref_clk_hz(void)
-{
-	return CONFIG_HPS_CLK_F2S_SDR_REF_HZ;
-}
diff --git a/arch/arm/mach-socfpga/wrap_sdram_config.c b/arch/arm/mach-socfpga/wrap_sdram_config.c
deleted file mode 100644
index c43c2423a0..0000000000
--- a/arch/arm/mach-socfpga/wrap_sdram_config.c
+++ /dev/null
@@ -1,322 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2015 Marek Vasut <marex@denx.de>
- */
-
-#include <common.h>
-#include <errno.h>
-#include <asm/arch/sdram.h>
-
-/* Board-specific header. */
-#include <qts/sdram_config.h>
-
-static const struct socfpga_sdram_config sdram_config = {
-	.ctrl_cfg =
-		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
-			SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
-			SDR_CTRLGRP_CTRLCFG_MEMBL_LSB)			|
-		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER <<
-			SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
-			SDR_CTRLGRP_CTRLCFG_ECCEN_LSB)			|
-		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
-			SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
-			SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
-			SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
-			SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
-			SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB),
-	.dram_timing1 =
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
-			SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
-			SDR_CTRLGRP_DRAMTIMING1_TAL_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
-			SDR_CTRLGRP_DRAMTIMING1_TCL_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
-			SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
-			SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
-			SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB),
-	.dram_timing2 =
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
-			SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
-			SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
-			SDR_CTRLGRP_DRAMTIMING2_TRP_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
-			SDR_CTRLGRP_DRAMTIMING2_TWR_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
-			SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB),
-	.dram_timing3 =
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
-			SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
-			SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
-			SDR_CTRLGRP_DRAMTIMING3_TRC_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
-			SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
-			SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB),
-	.dram_timing4 =
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
-			SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB)	|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
-			SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB),
-	.lowpwr_timing =
-		(CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
-			SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB)	|
-		(CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
-			SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB),
-	.dram_odt =
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ <<
-			SDR_CTRLGRP_DRAMODT_READ_LSB)			|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
-			SDR_CTRLGRP_DRAMODT_WRITE_LSB),
-	.extratime1 =
-	(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR <<
-			SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB)		|
-	(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC <<
-			SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB)		|
-(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP <<
-			SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB),
-	.dram_addrw =
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
-			SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS <<
-			SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
-			SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB)		|
-		((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
-			SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB),
-	.dram_if_width =
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<
-			SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB),
-	.dram_dev_width =
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<
-			SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB),
-	.dram_intr =
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN <<
-			SDR_CTRLGRP_DRAMINTR_INTREN_LSB),
-	.lowpwr_eq =
-		(CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK <<
-			SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB),
-	.static_cfg =
-		(CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
-			SDR_CTRLGRP_STATICCFG_MEMBL_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
-			SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB),
-	.ctrl_width =
-		(CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<
-			SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB),
-	.cport_width =
-		(CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<
-			SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB),
-	.cport_wmap =
-		(CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP <<
-			SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB),
-	.cport_rmap =
-		(CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP <<
-			SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB),
-	.rfifo_cmap =
-		(CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<
-			SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB),
-	.wfifo_cmap =
-		(CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<
-			SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB),
-	.cport_rdwr =
-		(CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<
-			SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB),
-	.port_cfg =
-		(CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<
-			SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB),
-	.fpgaport_rst = CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST,
-	.fifo_cfg =
-		(CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
-			SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
-			SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB),
-	.mp_priority =
-		(CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY <<
-			SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB),
-	.mp_weight0 =
-		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
-			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB),
-	.mp_weight1 =
-		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
-			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) |
-		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
-			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB),
-	.mp_weight2 =
-		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
-			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB),
-	.mp_weight3 =
-		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
-			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB),
-	.mp_pacing0 =
-		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
-			SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB),
-	.mp_pacing1 =
-		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
-			SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB) |
-		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
-			SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB),
-	.mp_pacing2 =
-		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
-			SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB),
-	.mp_pacing3 =
-		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
-			SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB),
-	.mp_threshold0 =
-		(CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
-			SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB),
-	.mp_threshold1 =
-		(CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
-			SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB),
-	.mp_threshold2 =
-		(CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
-			SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB),
-	.phy_ctrl0 = CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0,
-};
-
-static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = {
-	.activate_0_and_1		= RW_MGR_ACTIVATE_0_AND_1,
-	.activate_0_and_1_wait1		= RW_MGR_ACTIVATE_0_AND_1_WAIT1,
-	.activate_0_and_1_wait2		= RW_MGR_ACTIVATE_0_AND_1_WAIT2,
-	.activate_1			= RW_MGR_ACTIVATE_1,
-	.clear_dqs_enable		= RW_MGR_CLEAR_DQS_ENABLE,
-	.guaranteed_read		= RW_MGR_GUARANTEED_READ,
-	.guaranteed_read_cont		= RW_MGR_GUARANTEED_READ_CONT,
-	.guaranteed_write		= RW_MGR_GUARANTEED_WRITE,
-	.guaranteed_write_wait0		= RW_MGR_GUARANTEED_WRITE_WAIT0,
-	.guaranteed_write_wait1		= RW_MGR_GUARANTEED_WRITE_WAIT1,
-	.guaranteed_write_wait2		= RW_MGR_GUARANTEED_WRITE_WAIT2,
-	.guaranteed_write_wait3		= RW_MGR_GUARANTEED_WRITE_WAIT3,
-	.idle				= RW_MGR_IDLE,
-	.idle_loop1			= RW_MGR_IDLE_LOOP1,
-	.idle_loop2			= RW_MGR_IDLE_LOOP2,
-	.init_reset_0_cke_0		= RW_MGR_INIT_RESET_0_CKE_0,
-	.init_reset_1_cke_0		= RW_MGR_INIT_RESET_1_CKE_0,
-	.lfsr_wr_rd_bank_0		= RW_MGR_LFSR_WR_RD_BANK_0,
-	.lfsr_wr_rd_bank_0_data		= RW_MGR_LFSR_WR_RD_BANK_0_DATA,
-	.lfsr_wr_rd_bank_0_dqs		= RW_MGR_LFSR_WR_RD_BANK_0_DQS,
-	.lfsr_wr_rd_bank_0_nop		= RW_MGR_LFSR_WR_RD_BANK_0_NOP,
-	.lfsr_wr_rd_bank_0_wait		= RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
-	.lfsr_wr_rd_bank_0_wl_1		= RW_MGR_LFSR_WR_RD_BANK_0_WL_1,
-	.lfsr_wr_rd_dm_bank_0		= RW_MGR_LFSR_WR_RD_DM_BANK_0,
-	.lfsr_wr_rd_dm_bank_0_data	= RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
-	.lfsr_wr_rd_dm_bank_0_dqs	= RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
-	.lfsr_wr_rd_dm_bank_0_nop	= RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
-	.lfsr_wr_rd_dm_bank_0_wait	= RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
-	.lfsr_wr_rd_dm_bank_0_wl_1	= RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1,
-	.mrs0_dll_reset			= RW_MGR_MRS0_DLL_RESET,
-	.mrs0_dll_reset_mirr		= RW_MGR_MRS0_DLL_RESET_MIRR,
-	.mrs0_user			= RW_MGR_MRS0_USER,
-	.mrs0_user_mirr			= RW_MGR_MRS0_USER_MIRR,
-	.mrs1				= RW_MGR_MRS1,
-	.mrs1_mirr			= RW_MGR_MRS1_MIRR,
-	.mrs2				= RW_MGR_MRS2,
-	.mrs2_mirr			= RW_MGR_MRS2_MIRR,
-	.mrs3				= RW_MGR_MRS3,
-	.mrs3_mirr			= RW_MGR_MRS3_MIRR,
-	.precharge_all			= RW_MGR_PRECHARGE_ALL,
-	.read_b2b			= RW_MGR_READ_B2B,
-	.read_b2b_wait1			= RW_MGR_READ_B2B_WAIT1,
-	.read_b2b_wait2			= RW_MGR_READ_B2B_WAIT2,
-	.refresh_all			= RW_MGR_REFRESH_ALL,
-	.rreturn			= RW_MGR_RETURN,
-	.sgle_read			= RW_MGR_SGLE_READ,
-	.zqcl				= RW_MGR_ZQCL,
-
-	.true_mem_data_mask_width	= RW_MGR_TRUE_MEM_DATA_MASK_WIDTH,
-	.mem_address_mirroring		= RW_MGR_MEM_ADDRESS_MIRRORING,
-	.mem_data_mask_width		= RW_MGR_MEM_DATA_MASK_WIDTH,
-	.mem_data_width			= RW_MGR_MEM_DATA_WIDTH,
-	.mem_dq_per_read_dqs		= RW_MGR_MEM_DQ_PER_READ_DQS,
-	.mem_dq_per_write_dqs		= RW_MGR_MEM_DQ_PER_WRITE_DQS,
-	.mem_if_read_dqs_width		= RW_MGR_MEM_IF_READ_DQS_WIDTH,
-	.mem_if_write_dqs_width		= RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
-	.mem_number_of_cs_per_dimm	= RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
-	.mem_number_of_ranks		= RW_MGR_MEM_NUMBER_OF_RANKS,
-	.mem_virtual_groups_per_read_dqs =
-		RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
-	.mem_virtual_groups_per_write_dqs =
-		RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS,
-};
-
-static const struct socfpga_sdram_io_config io_config = {
-	.delay_per_dchain_tap		= IO_DELAY_PER_DCHAIN_TAP,
-	.delay_per_dqs_en_dchain_tap	= IO_DELAY_PER_DQS_EN_DCHAIN_TAP,
-	.delay_per_opa_tap_lo		= IO_DELAY_PER_OPA_TAP & 0xff,
-	.delay_per_opa_tap_hi		= (IO_DELAY_PER_OPA_TAP << 8) & 0xff,
-	.dll_chain_length		= IO_DLL_CHAIN_LENGTH,
-	.dqdqs_out_phase_max		= IO_DQDQS_OUT_PHASE_MAX,
-	.dqs_en_delay_max		= IO_DQS_EN_DELAY_MAX,
-	.dqs_en_delay_offset		= IO_DQS_EN_DELAY_OFFSET,
-	.dqs_en_phase_max		= IO_DQS_EN_PHASE_MAX,
-	.dqs_in_delay_max		= IO_DQS_IN_DELAY_MAX,
-	.dqs_in_reserve			= IO_DQS_IN_RESERVE,
-	.dqs_out_reserve		= IO_DQS_OUT_RESERVE,
-	.io_in_delay_max		= IO_IO_IN_DELAY_MAX,
-	.io_out1_delay_max		= IO_IO_OUT1_DELAY_MAX,
-	.io_out2_delay_max		= IO_IO_OUT2_DELAY_MAX,
-	.shift_dqs_en_when_shift_dqs	= IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS,
-};
-
-static const struct socfpga_sdram_misc_config misc_config = {
-	.afi_rate_ratio			= AFI_RATE_RATIO,
-	.calib_lfifo_offset		= CALIB_LFIFO_OFFSET,
-	.calib_vfifo_offset		= CALIB_VFIFO_OFFSET,
-	.enable_super_quick_calibration	= ENABLE_SUPER_QUICK_CALIBRATION,
-	.max_latency_count_width	= MAX_LATENCY_COUNT_WIDTH,
-	.read_valid_fifo_size		= READ_VALID_FIFO_SIZE,
-	.reg_file_init_seq_signature_ll	= REG_FILE_INIT_SEQ_SIGNATURE & 0xff,
-	.reg_file_init_seq_signature_lh	= (REG_FILE_INIT_SEQ_SIGNATURE >> 8) & 0xff,
-	.reg_file_init_seq_signature_hl	= (REG_FILE_INIT_SEQ_SIGNATURE >> 16) & 0xff,
-	.reg_file_init_seq_signature_hh	= (REG_FILE_INIT_SEQ_SIGNATURE >> 24) & 0xff,
-	.tinit_cntr0_val		= TINIT_CNTR0_VAL,
-	.tinit_cntr1_val		= TINIT_CNTR1_VAL,
-	.tinit_cntr2_val		= TINIT_CNTR2_VAL,
-	.treset_cntr0_val		= TRESET_CNTR0_VAL,
-	.treset_cntr1_val		= TRESET_CNTR1_VAL,
-	.treset_cntr2_val		= TRESET_CNTR2_VAL,
-};
-
-const struct socfpga_sdram_config *socfpga_get_sdram_config(void)
-{
-	return &sdram_config;
-}
-
-void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem)
-{
-	*init = ac_rom_init;
-	*nelem = ARRAY_SIZE(ac_rom_init);
-}
-
-void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem)
-{
-	*init = inst_rom_init;
-	*nelem = ARRAY_SIZE(inst_rom_init);
-}
-
-const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void)
-{
-	return &rw_mgr_config;
-}
-
-const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void)
-{
-	return &io_config;
-}
-
-const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void)
-{
-	return &misc_config;
-}
