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[U-Boot,RFC,v2,15/18] arm: socfpga: gen5: load CLK config from devicetree

Message ID 20191015201032.20156-16-simon.k.r.goldschmidt@gmail.com
State Deferred, archived
Delegated to: Simon Goldschmidt
Headers show
Series arm: socfpga: gen5: move to DM | expand

Commit Message

Simon Goldschmidt Oct. 15, 2019, 8:10 p.m. UTC 
Instead of using ad-hoc code in arch/arm, load clock config from devicetree.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---

Changes in v2: None

 drivers/clk/altera/clk-gen5.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/drivers/clk/altera/clk-gen5.c b/drivers/clk/altera/clk-gen5.c
index e8f435a798..a5425b7424 100644
--- a/drivers/clk/altera/clk-gen5.c
+++ b/drivers/clk/altera/clk-gen5.c
@@ -136,7 +136,13 @@  static int socfpga_gen5_clk_init(struct udevice *dev)
 	struct socfpga_gen5_clk_platdata *plat = dev_get_platdata(dev);
 	const struct socfpga_clock_manager *clock_manager_base =
 		(const struct socfpga_clock_manager *)plat->regs;
-	const struct cm_config *cfg = cm_get_default_config();
+	const struct cm_config *cfg = (const struct cm_config *)
+		dev_read_u8_array_ptr(dev, "altr,clk-mgr-cfg", sizeof(*cfg));
+
+	if (!cfg) {
+		dev_dbg(dev, "Failed to load CLK config\n");
+		return -EINVAL;
+	}
 
 	/* Start by being paranoid and gate all sw managed clocks */